An edition of Design of cost-efficient interconnect processing units (2008)

Design of cost-efficient interconnect processing units

the Spidergon STNoC

by , , , , and

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Last edited by MARC Bot
December 15, 2022 | History
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An edition of Design of cost-efficient interconnect processing units (2008)

Design of cost-efficient interconnect processing units

the Spidergon STNoC

by , , , , and

  • 0 Ratings
  • 0 Want to read
  • 0 Currently reading
  • 0 Have read

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Publish Date
Publisher
Taylor & Francis
Language
English

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Subjects
ST Microelectronics, Networks on a chip, Microprocessors, Microelectronics, Réseaux sur puce, COMPUTERS, Hardware, Mainframes & Minicomputers, Mikroprocessorer

Showing 8 featured editions. View all 8 editions?

Edition Availability
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Libraries near you: WorldCat
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Libraries near you: WorldCat
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Libraries near you: WorldCat
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2018, Taylor & Francis Group
in English
Libraries near you: WorldCat
Cover of: Design of cost-efficient interconnect processing units
Design of cost-efficient interconnect processing units: the Spidergon STNoC
2009, Taylor & Francis
in English
  • Not in Library
Libraries near you: WorldCat
Cover of: Design of cost-efficient interconnect processing units
Design of cost-efficient interconnect processing units: Spidergon STNoC
2009, Taylor & Francis
in English
Libraries near you: WorldCat
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc
2008, Taylor & Francis Group
in English
Libraries near you: WorldCat
Cover of: Design of Cost-Efficient Network-on-Chip Architectures
Design of Cost-Efficient Network-on-Chip Architectures: The STNoC (System-on-Chip Design and Technologies)
July 15, 2008, CRC
Hardcover in English
Libraries near you: WorldCat

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Book Details

Edition Notes

"A CRC title."

Includes bibliographical references and index.

Published in
Boca Raton
Series
System-on-chip design and technologies -- 2

Classifications

Dewey Decimal Class
004.1
Library of Congress
TK5105.546 .D47 2009

The Physical Object

Pagination
p. cm.

ID Numbers

Open Library
OL18725270M
ISBN 13
9781420044713
LCCN
2008026558
Library Thing
7233086
Goodreads
2427946

Source records

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December 15, 2022 Edited by MARC Bot import existing book
August 14, 2020 Edited by ImportBot import existing book
February 9, 2019 Created by MARC Bot import existing book