An edition of Design of cost-efficient interconnect processing units (2008)

Design of cost-efficient interconnect processing units

the Spidergon STNoC

by , , , , and

Design of cost-efficient interconnect process ...
Miltos D. Grammatikakis, Marce ...
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Last edited by MARC Bot
July 31, 2019 | History
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An edition of Design of cost-efficient interconnect processing units (2008)

Design of cost-efficient interconnect processing units

the Spidergon STNoC

by , , , , and

This edition doesn't have a description yet. Can you add one?

Publish Date
Publisher
Taylor & Francis
Language
English

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Subjects

ST Microelectronics, Networks on a chip, Microprocessors, Microelectronics, Réseaux sur puce, COMPUTERS, Hardware, Mainframes & Minicomputers, Mikroprocessorer
Edition Availability
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2018, Taylor & Francis Group
in English
Cover of: Design of cost-efficient interconnect processing units
Design of cost-efficient interconnect processing units: Spidergon STNoC
2009, Taylor & Francis
in English
Cover of: Design of cost-efficient interconnect processing units
Design of cost-efficient interconnect processing units: the Spidergon STNoC
2009, Taylor & Francis
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc
2008, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Network-on-Chip Architectures
Design of Cost-Efficient Network-on-Chip Architectures: The STNoC (System-on-Chip Design and Technologies)
July 15, 2008, CRC
Hardcover in English

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Book Details

Edition Notes

"A CRC title."

Includes bibliographical references and index.

Published in
Boca Raton
Series
System-on-chip design and technologies -- 2

Classifications

Dewey Decimal Class
004.1
Library of Congress
TK5105.546 .D47 2009

The Physical Object

Pagination
p. cm.

Edition Identifiers

Open Library
OL18725270M
ISBN 13
9781420044713
LCCN
2008026558
LibraryThing
7233086
Goodreads
2427946

Work Identifiers

Work ID
OL18600926W

Source records

Library of Congress MARC record
Library of Congress MARC record
Library of Congress MARC record
Library of Congress MARC record

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History

Download catalog record: RDF / JSON / OPDS | Wikipedia citation
July 31, 2019 Edited by MARC Bot associate edition with work OL18600926W
August 18, 2010 Edited by IdentifierBot added LibraryThing ID
April 16, 2010 Edited by bgimpertBot Added goodreads ID.
September 4, 2009 Edited by ImportBot Found a matching Library of Congress MARC record
October 19, 2008 Created by ImportBot Imported from Library of Congress MARC record