An edition of Design of cost-efficient interconnect processing units (2008)

Design of Cost-Efficient Network-on-Chip Architectures

The STNoC (System-on-Chip Design and Technologies)

by , , , , and

Cover of: Design of Cost-Efficient Network-on-Chip Architectures by Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Miltos D. Grammatikakis, Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi
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Last edited by MARC Bot
December 15, 2022 | History
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An edition of Design of cost-efficient interconnect processing units (2008)

Design of Cost-Efficient Network-on-Chip Architectures

The STNoC (System-on-Chip Design and Technologies)

by , , , , and

This edition doesn't have a description yet. Can you add one?

Publish Date
Publisher
CRC
Language
English

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Subjects

ST Microelectronics, Networks on a chip, Microprocessors, Microelectronics, Réseaux sur puce, COMPUTERS, Hardware, Mainframes & Minicomputers, Mikroprocessorer
Edition Availability
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2020, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC
2018, Taylor & Francis Group
in English
Cover of: Design of cost-efficient interconnect processing units
Design of cost-efficient interconnect processing units: the Spidergon STNoC
2009, Taylor & Francis
in English
Cover of: Design of cost-efficient interconnect processing units
Design of cost-efficient interconnect processing units: Spidergon STNoC
2009, Taylor & Francis
in English
Cover of: Design of Cost-Efficient Interconnect Processing Units
Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc
2008, Taylor & Francis Group
in English
Cover of: Design of Cost-Efficient Network-on-Chip Architectures
Design of Cost-Efficient Network-on-Chip Architectures: The STNoC (System-on-Chip Design and Technologies)
July 15, 2008, CRC
Hardcover in English

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Book Details

Classifications

Library of Congress
TK7895.E42, TK5105.546 .D47 2009, TK5105.546 .D47 2009eb

The Physical Object

Format
Hardcover

Edition Identifiers

Open Library
OL11816458M
ISBN 10
1420044710
ISBN 13
9781420044713
LCCN
2008026558
OCLC/WorldCat
297170427
LibraryThing
7233086
Goodreads
2427946

Work Identifiers

Work ID
OL18600926W

Source records

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History

Download catalog record: RDF / JSON / OPDS | Wikipedia citation
December 15, 2022 Edited by MARC Bot import existing book
December 20, 2020 Edited by MARC Bot import existing book
October 12, 2020 Edited by ImportBot import existing book
August 14, 2020 Edited by ImportBot import existing book
April 30, 2008 Created by an anonymous user Imported from amazon.com record