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Subjects
Plug and play (Computer architecture), Systems on a chip, Testing, Electronic devices & materials, General Theory of Computing, Science/Mathematics, Electronics - General, Technology, Electronic Measurements, Integrated Circuits, Technology & Industrial Arts, Plug and play (Computer archit, Engineering - Electrical & Electronic, Computer Engineering, Electronics - Circuits - Integrated, Computers : Computer Engineering, Technology / Electronics / Circuits / General, Technology / Engineering / Electrical, Technology : Electronics - Circuits - Integrated, Computer Architecture - General, Computer architectureShowing 2 featured editions. View all 2 editions?
Edition | Availability |
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1
Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) (Frontiers in Electronic Testing)
May 1, 2002, Springer
Hardcover
in English
- 1 edition
1402071191 9781402071195
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WorldCat
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2
Test resource partitioning for system-on-a-chip
2002, Kluwer Academic Publishers
in English
1402071191 9781402071195
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Libraries near you:
WorldCat
|
Book Details
First Sentence
"Test resource partitioning (TRP) for a system-on-a-chip (SOC) refers to the process of partitioning monolithic test resources, such as the test data set or the top-level test access mechanism (TAM) into sub-components that can be optimized for significant gains in test resource utilization."
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- Created April 29, 2008
- 5 revisions
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July 31, 2019 | Edited by MARC Bot | associate edition with work OL8638073W |
April 24, 2010 | Edited by Open Library Bot | Fixed duplicate goodreads IDs. |
April 16, 2010 | Edited by bgimpertBot | Added goodreads ID. |
April 14, 2010 | Edited by Open Library Bot | Linked existing covers to the edition. |
April 29, 2008 | Created by an anonymous user | Imported from amazon.com record |