An edition of CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (2010)

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test

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CMOS SRAM Circuit Design and Parametric Test ...
Andrei Pavlov, Manoj Sachdev, ...
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Last edited by ImportBot
October 2, 2021 | History
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An edition of CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (2010)

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

Process-Aware SRAM Design and Test

by and

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Publish Date
Publisher
Springer
Language
English
Pages
194

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Subjects

Metal oxide semiconductors, complementary, Computer storage devices, Electronics
Edition Availability
Cover of: CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test
2010, Springer
in English

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Book Details

Classifications

Library of Congress
TK7888.4TK7895.M4

The Physical Object

Number of pages
194
Weight
0.332

Edition Identifiers

Open Library
OL34371094M
ISBN 13
9789048178551

Work Identifiers

Work ID
OL25615555W

Source records

Better World Books record

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October 2, 2021 Created by ImportBot Imported from Better World Books record