An edition of Verification by error modeling
(2003)
Verification by error modeling
using testing techniques in hardware verification
by Katarzyna Radecka
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Previews available in: English
Subjects
Computer-aided design, Error analysis (Mathematics), Integrated circuits, Verification, Very large scale integration, TECHNOLOGY & ENGINEERING, Circuits, COMPUTERS, Logic Design, Engineering, Logic, VLSI & ULSI, Electrical engineering, Electronics, Integrated circuits, very large scale integration, Computer software, verification, Error analysis (mathematics)| Edition | Availability |
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1
Verification by Error Modeling: Using Testing Techniques In Hardware Verification
Dec 07, 2010, Springer
paperback
1441954023 9781441954022
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2
Verification by Error Modeling: Using Testing Techniques in Hardware Verification
2006, Springer London, Limited
in English
030648739X 9780306487392
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3
Verification by error modeling: using testing techniques in hardware verification
2003, Kluwer Academic Publishers
in English
1402076525 9781402076527
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Book Details
Edition Notes
Includes bibliographical references and index.
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- Created October 21, 2008
- 13 revisions
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| January 8, 2023 | Edited by MARC Bot | import existing book |
| December 5, 2022 | Edited by ImportBot | import existing book |
| December 8, 2020 | Edited by MARC Bot | import existing book |
| October 8, 2020 | Edited by ImportBot | import existing book |
| October 21, 2008 | Created by ImportBot | Imported from Library of Congress MARC record |