Dedication
xxi
v
Table of Contents vii
About the Author xv
List of Examples
Foreword
Acknowledgments
Introduction
Intended Audience:
The IEEE 1364 Verilog PLI standard
The history of the Verilog PLI
1985: The TF routines
1988: The ACC routines
1990: The OVI PLI 1.0 standard
1993: The OVI PLI 2.0 standard
1995: The IEEE 1364-1995 PLI standard and VPI routines
2001: The IEEE 1364-2001 PLI standard
Ambiguities in the Verilog PLI standard
Organization of this book
About the PLI examples in this book
Other sources of information
xvii
xxiii
1
1
2
2
2
3
3
3
4
4
5
5
6
7
viii Using The Verilog PLI
Part One: The VPI Portion of the Verilog PLI Standard
Creating PLI Applications Using VPI Routines
1.1
1.2
1.3
1.4
1.5
The capabilities of the Verilog PLI
General steps to create a PLI application
User-defined system tasks and system functions
The $hello PLI application example
The $show_value PLI application example
Interfacing VPI Applications to Verilog Simulators
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
General PLI terms as used in this book
System tasks and system functions
Instantiated Verilog designs
How PLI applications work
calltf routines
compiletf routines
sizetf routines
VPI Simulation callback routines
PLI routine inputs and outputs
2.10
2.11
2.12
2.13
A complete system function example — $pow
Interfacing PLI applications to Verilog simulators
Using the VPI user_data field
Compiling and linking PLI applications
How to Use the VPI Routines
3.10
3.11
3.12
3.13
3.14
3.15
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Specification of $show_all_nets and $show_all_signals
The VPI routine library
Advantages of the VPI library
Verilog HDL objects
Obtaining object handles
Accessing the arguments of a system task/function
Printing messages from VPI applications
Accessing object properties
Reading the logic values of Verilog objects
Reading the current simulation time
Controlling simulation from PLI applications
A complete PLI application using VPI routines
Obtaining handles for reg and variable data types
Obtaining a handle to the current hierarchy scope
Obtaining handles to multiple task/function arguments
11
11
13
14
15
19
27
27
29
31
34
36
37
39
41
42
42
46
51
53
55
55
56
57
59
62
65
66
67
69
71
73
74
78
85
91
CHAPTER 1:
CHAPTER 2:
CHAPTER 3:
ix
CHAPTER 4: Details about the VPI Routine Library
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
PLI application performance considerations
The VPI string buffer
VPI error handling
VPI object diagrams
Obtaining handles for objects
System task and system function objects
Storing data for each instance of a system task/function
Traversing Verilog hierarchy using object relationships
Writing messages to files
Reading and using simulation times
User-defined invocation options
Controlling Simulations
CHAPTER 5: Reading and Modifying Values Using VPI Routines
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Accessing objects which have logic values
Reading object logic values
Writing values to Verilog objects
Returning logic values of system functions
Reading and writing automatic variables
Reading IEEE 1364-2001 Verilog attributes
Reading IEEE 1364-1995 specparam constant attributes
Accessing Verilog net, reg, memory and arrays
Reading and modifying delay values
CHAPTER 6: Synchronizing to Simulations Using VPI Callbacks
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
PLI application callbacks
Sharing information between callback routines
Registering simulation callback routines
Removing scheduled callbacks
Avoiding memory leaks with simulation callbacks
Simulation action-related callbacks
Simulation time-related callbacks
Simulation event-related callbacks
CHAPTER 7: Interfacing to C Models Using VPI Routines
7.1
7.2
7.3
7.4
7.5
7.6
How to interface C models with Verilog simulations
Creating the C language model
A C model example
Creating a Verilog shell module
Creating a combinational logic interface to a C model
Creating a sequential logic interface to a C model
97
98
99
100
102
106
116
122
128
137
140
144
148
151
151
152
173
177
180
182
182
185
186
197
197
198
201
204
205
206
216
235
241
242
244
245
248
249
256
4.10
4.11
4.12
Using The Verilog PLI
7.7
7.8
7.9
7.10
Synchronizing with the end of a simulation time step
Synchronizing with a future simulation time step
Allocating storage within a C model
Representing propagation delays in a C model
259
263
263
267
Part Two: The TF/ACC Portion of the Verilog PLI Standard
CHAPTER 8: Creating PLI Applications Using TF and ACC Routines 273
8.1
8.2
8.3
8.4
8.5
The capabilities of the Verilog PLI
General steps to create a PLI application
User-defined system tasks and system functions
The $hello PLI application example
The $show_value PLI application example
273
275
276
277
280
CHAPTER 9: Interfacing TF/ACC Applications to Verilog Simulators 287
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
General PLI terms as used in this book
System tasks and system functions
Instantiated Verilog designs
How PLI applications work
calltf routines
checktf routines
sizetf routines
misctf routines
PLI routine inputs and outputs
A complete system function example — $pow
Interfacing PLI applications to Verilog simulators
Using the user_data field
Compiling and linking PLI applications
287
289
291
294
296
297
299
300
302
303
305
310
311
CHAPTER 10: How to Use the TF Routines 313
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
The TF Library
System tasks and system functions
The PLI string buffer
Controlling simulation
Printing messages
Checking system task/function arguments
The TF work area
Reading and using simulation times
Reading simulation invocation options
Utility TF routines
A complete PLI application using TF Routines
313
315
318
319
319
323
325
329
334
335
337
x
xi
CHAPTER 11: Reading and Writing Values Using TF Routines 341
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Working with a 4-logic value, multiple strength level system
How the PLI writes values into Verilog
Reading and writing 2-state values
Reading and writing 4-state logic values using C strings
Reading Verilog strings
Reading and writing 4-state values using aval/bval encoding
Reading 4-state logic values with strengths
Reading from and writing into Verilog memory arrays
341
342
344
349
357
358
371
378
CHAPTER 12: Synchronizing to Simulations Using Misctf Routines 401
12.1
12.2
12.3
12.4
12.5
12.6
12.7
The purpose of the misctf routine
Automatic callbacks for simulation events
Application scheduled callbacks at the end of a time step
Application-scheduled callbacks at a future simulation time
System task/function argument value change callbacks
Simulation save and restart checkpoint files
A complete example of using misctf routine callbacks
401
405
408
414
418
422
424
CHAPTER 13: Interfacing to C Models Using TF Routines 431
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10
How to interface C models with Verilog simulations
Creating the C language model
A C model example
Creating a Verilog shell module
Creating a combinational logic interface to a C model
Creating a sequential logic interface to a C model
Synchronizing with the end of a simulation time step
Synchronizing with a future simulation time step
Allocating storage within a C model
Representing propagation delays in a C model
432
434
435
437
439
445
448
451
451
455
CHAPTER 14: How to Use the ACC Routines 459
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
Specification of $show_all_nets and $show_all_signals
The ACC routine library
Advantages of the ACC library
Verilog HDL objects
ACC handle routines
ACC next routines
Accessing object types and fulltypes
Accessing the names of objects
The ACC string buffer
Reading the logic values of Verilog objects
459
460
462
463
465
466
468
470
471
472
xii Using The Verilog PLI
14.11
14.12
14.13
14.14
A complete PLI application using ACC routines
Accessing handles for reg and variable data types
Obtaining handles to the current hierarchy scope
Obtaining handles to multiple task/function arguments
473
475
479
483
CHAPTER 15: Details on the ACC Routine Library 487
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
PLI application performance considerations
Initializing and configuring ACC routines
ACC routine error handling
Using ACC object diagrams
Using ACC handle routines
Using ACC next routines
Traversing Verilog hierarchy using object relationships
Traversing hierarchy across module ports
Identifying modules and library cells
15.10
15.11
15.12
15.13
15.14
15.15
Accessing loads and drivers
Accessing model timing
Counting the number of objects
Collecting and maintaining lists of object handles
Obtaining object handles using an object’s name
Comparing ACC handles
487
489
492
494
498
499
501
506
512
514
516
523
525
528
532
CHAPTER 16: Reading and Modifying Values Using ACC Routines
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
16.9
16.10
16.11
16.12
16.13
16.14
16.15
Using ACC fetch routines
Reading object type properties
Accessing an object’s source code location
Reading the simulation invocation commands
Accessing objects in simulation which have logic values
Reading the values of system task/function arguments
Reading object logic values
Writing values into Verilog objects
Returning logic values of system functions
Reading module time scale information
Reading delay values
Writing delay values into an object
Reading parameter constant values
Using constants as model attributes
Reading and modifying path pulse controls
535
536
538
542
544
546
547
552
564
570
572
575
584
590
592
594
CHAPTER 17: Using the Value Change Link (VCL) 601
17.1
17.2
An overview of the VCL routines
Adding and removing VCL flags on Verilog objects
601
602
xiii
17.3
17.4
17.5
Using the VCL consumer routine
An example of using Value Change Link routines
Obtaining object handles from the consumer routine
605
608
609
CHAPTER 18: Interfacing to C Models Using ACC Routines 611
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
18.10
How to interface C models with Verilog simulations
Creating the C language model
A C model example
Creating a Verilog shell module
Creating a combinational logic interface to a C model
Creating a sequential logic interface to a C model
Synchronizing with the end of a simulation time step
Synchronizing with a future simulation time step
Allocating storage within a C model
Representing propagation delays in a C model
612
614
615
618
619
624
627
631
631
637