An edition of SPARC Architecture, Assembly Language Programming, and C
(1994)
SPARC architecture, assembly language programming, and C
2nd ed.
by Richard P. Paul
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Last edited by Tom Morris
November 22, 2024 | History
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| Edition | Availability |
|---|---|
1
SPARC architecture, assembly language programming, and C
2000, Prentice Hall
in English
- 2nd ed.
0130255963 9780130255969
|
aaaa
|
2
SPARC Architecture, Assembly Language Programming, and C (2nd Edition)
July 29, 1999, Prentice Hall
Paperback
in English
- 2nd edition
0130255963 9780130255969
|
zzzz
|
3
SPARC Architecture, Assembly Language Programming, and C (2nd Edition)
July 29, 1999, Prentice Hall
in English
0130255963 9780130255969
|
zzzz
|
4
SPARC architecture, assembly language programming, and C
1994, Prentice Hall
in English
0138768897 9780138768898
|
zzzz
|
Book Details
Table of Contents
1
Computer -- 1 -- 1.2
Calculators -- 1 -- 1.2.1
Stack Calculators -- 2 -- 1.2.2
Use of Registers -- 4 -- 1.2.3
Programmable Calculators -- 6 -- 1.2.4
Machine Language Programming -- 8 -- 1.3
m4: The Macro Processor -- 9 -- 1.3.1
Macros with Arguments -- 10 -- 1.3.2
Memory Location -- 13 -- 1.3.3
Conditionals and Branching -- 14 -- 1.4
Von Neumann Machine -- 17 -- 1.5
Stack Machine -- 17 -- 1.6
Java Virtual Machine -- 20 -- 1.7
Accumulator Machines -- 30 -- 1.8
Load/Store Machines -- 33 -- 1.9
Assemblers -- 39 -- 2
Sparc Architecture -- 51 -- 2.2
Registers -- 51 -- 2.3
SPARC Assembly Language Programming -- 52 -- 2.5
Pipelining -- 56 -- 2.6
Example Continued -- 61 -- 2.7
Debugger gdb -- 63 -- 2.8
Filling Delay Slots -- 67 -- 2.9
Branching -- 70 -- 2.9.1
Testing -- 70 -- 2.9.2
Branches -- 71 -- 2.10
Control Statements -- 77 -- 2.10.1
While -- 78 -- 2.10.2
Do -- 80 -- 2.10.3
For -- 82 -- 2.10.4
If Then -- 83 -- 2.10.5
If Else -- 85 -- 2.11
Annulled Unconditional Branch -- 88 -- 3
Digital Logic and Binary Numbers -- 97 -- 3.1
Binary Hardware Devices -- 97 -- 3.2
Decimal and Binary Number Systems -- 99 -- 3.2.1
Octal and Hexadecimal Numbers -- 100 -- 3.2.2
Converting from Decimal to Binary -- 102 -- 3.2.3
Converting from Binary to Decimal -- 104 -- 3.3
ASCII Representation of Characters -- 105 -- 3.4
Bitwise Logical Operations -- 105 -- 3.4.1
Synthetic Instructions Using %g0 -- 109 -- 3.4.2
Flags -- 111 -- 4
Binary Arithmetic -- 115 -- 4.2
Binary Numbers and Addition -- 115 -- 4.3
Half and Full Adders -- 117 -- 4.4
Modulus Arithmetic -- 117 -- 4.5
Subtraction -- 119 -- 4.6
Two's Complement Number Branching Conditions -- 122 -- 4.6.1
Shifting -- 123 -- 4.7
Unsigned Arithmetic -- 124 -- 4.8
Unsigned Number Branching Conditions -- 124 -- 4.9
Condition Code Tests -- 125 -- 4.10
Multiplication -- 125 -- 4.10.1
SPARC mulscc Instruction -- 131 -- 4.11
Division -- 134 -- 4.12
Extended Precision Arithmetic -- 139 -- 4.12.1
Addition of Extended Precision Numbers -- 139 -- 4.12.2
Subtraction of Extended Precision Numbers -- 139 -- 4.12.3
Multiplication of Extended Precision Numbers -- 141 -- 5
Stack -- 151 -- 5.1
Memory -- 151 -- 5.2.1
Frame Pointer -- 154 -- 5.3
Addressing Stack Variables -- 155 -- 5.3.1
Load Instructions -- 156 -- 5.3.2
Store Instructions -- 157 -- 5.4
Defining Stack Variable Offsets -- 157 -- 5.6
One-Dimensional Arrays -- 167 -- 5.7
Improvements to the Code -- 173 -- 6
Data Structures -- 181 -- 6.2
Array Storage and Addressing -- 181 -- 6.3
Multidimensional Arrays -- 182 -- 6.3.1
Lower Bounds Different from Zero -- 183 -- 6.3.2
Array Bound Checking -- 185 -- 6.4
Address Arithmetic -- 187 -- 6.5
Structures -- 190 -- 6.6
Structures as Automatic Variables -- 193 -- 6.6.1
Nested Structures -- 194 -- 7
Subroutines -- 203 -- 7.2
Open Subroutines -- 204 -- 7.3
Register Saving -- 204 -- 7.4
Subroutine Linkage -- 208 -- 7.5
Arguments to Subroutines -- 209 -- 7.7
Return Values -- 217 -- 7.8
Subroutines with Many Arguments -- 220 -- 7.9
Leaf Subroutines -- 221 -- 7.10
Pointers as Arguments to Subroutines -- 224 -- 8
Machine Instructions -- 231 -- 8.2
Instruction Decode -- 231 -- 8.3
Format Three Instructions -- 232 -- 8.4
Format One Instruction: The call Instruction -- 237 -- 8.5
Format Two Instructions -- 237 -- 8.5.1
Branch Instructions -- 238 -- 8.5.2
Loading 32-Bit Constants -- 242 -- 9
External Data and Text -- 247 -- 9.2
External Variables -- 247 -- 9.3
Text Section -- 248 -- 9.4
Data Section -- 248 -- 9.4.1
ASCII Data -- 252 -- 9.5
Pointers -- 253 -- 9.6
.Bss Section -- 254 -- 9.7
Switch Statement -- 255 -- 9.8
Relocation and Linking with Other Code -- 257 -- 9.9
Makefiles -- 261 -- 9.10
C Command Line Arguments -- 262 -- 10
Input/Output -- 271 -- 10.2
Memory Mapped I/O -- 271 -- 10.3
Character Devices -- 272 -- 10.4
Programmed I/O -- 272 -- 10.5
Interrupt-Driven I/O -- 275 -- 10.6
Block Devices -- 277 -- 10.7
Directory Devices -- 277 -- 10.8
Input/Output Processors -- 278 -- 10.9
System I/O -- 278 -- 11
Floating-Pointg -- 283 -- 11.2
Fixed Binary Point Numbers -- 284 -- 11.3
Scientific Notation -- 285 -- 11.4
Floating-Point -- 289 -- 11.5
Floating-Point Processor -- 290 -- 11.6
A Floating-Point Program -- 293 -- 11.6.1
Debugging Single Presision Floating-Point Code -- 295 -- 11.6.2
An Improved Version of the Code -- 296 -- 11.7
Floating NaNs -- 299 -- 11.8
Subnormal Numbers -- 299 -- 11.9
Extended Precision Floating-Point -- 300 -- 11.10
Debugging Floating Double Programs -- 304 -- 11.11
Floating Quad Format -- 309 -- 11.12
Function Calls -- 310 -- 11.13
Tagged Arithmetic -- 312 -- 11.13.1
Lisp -- 313 -- 12
Traps and Exceptions -- 329 -- 12.2
Processor State Registers -- 330 -- 12.2.1
Processor State Register -- 331 -- 12.2.2
Window Invalid Mask Register -- 331 -- 12.2.3
Trap Base Register -- 332 -- 12.2.4
Floating-Point Processor State Register -- 332 -- 12.3
Traps -- 333 -- 12.4
Window Traps -- 337 -- 13
Memory Management -- 347 -- 13.2
Virtual Memory and Paging -- 348 -- 13.3
Page Descriptor Cache -- 355 -- 13.4
Cache Memory -- 356 -- 13.5
Context Switching -- 357 -- 14
Other Architectures -- 359 -- 14.2
PDP-11 -- 360 -- 14.3
VAX-11 -- 366 -- 14.4
MIPS Architecture -- 373 -- 15
Ultra Sparc -- 379 -- 15.2
64-Bit Virtual Memory Addresses -- 379 -- 15.3
Superscalar Execution -- 382 -- 15.3.1
Branch Prediction -- 384 -- 15.3.2
Branch on Integer Register -- 385 -- 15.3.3
Multiple Floating-Point Condition Codes -- 386 -- 15.3.4
Move Register on Condition -- 387 -- 15.4
Instruction and Data Prefetching -- 391 -- 15.5
Nonfaulting Loads -- 391 -- 15.6
Changes to Supervisor Mode -- 393 -- A
Macro Definitions -- 395 -- B
Register Name Macro Definitions -- 399 -- C
Multiplication by Constants -- 401 -- C.2
m4 Built-in Macros -- 401 -- C.3
Conversion to Binary -- 403 -- C.4
Conversion to a Base 31 Number -- 405 -- C.5
Instruction Generation -- 406 -- D
User Mode Machine Instructions -- 409 -- D.1
Syntax -- 409 -- D.2
Arithmetic Instructions -- 410 -- D.3
Logical Instructions -- 418 -- D.4
Shift Instructions -- 424 -- D.5
Load Instructions -- 425 -- D.6
Store Instructions -- 427 -- D.7
Integer Branch Instructions -- 429 -- D.8
Trap Instructions -- 438 -- D.9
Control Instructions -- 447 -- D.10
Floating-Point Instructions -- 450 -- D.11
Floating-Point Branch Instructions -- 465 -- E
Synthetic Instructions and Pseudo-Ops -- 473 -- F
Instructions Sorted Alphabetically -- 479 -- G
Powers of 2 -- 483 -- H
Macro Language Processor m4-- 485.
Edition Notes
Includes bibliographical references (p. 489-491) and index.
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| November 22, 2024 | Edited by Tom Morris | Merge works |
| November 16, 2020 | Edited by MARC Bot | import existing book |
| August 18, 2020 | Edited by ImportBot | import existing book |
| December 4, 2010 | Edited by Open Library Bot | Added subjects from MARC records. |
| December 10, 2009 | Created by WorkBot | add works page |