Integrated circuit design with sub-100nm technology requires closer attention to the effect of process variations and their impact on circuit timing and timing yield. In this work, we introduce a statistical static timing analysis technique that is based on a timing yield model. This technique preserves existing methodology by selecting a "device file setting" or "virtual corner" that takes into account within-die statistical variations. If this corner is used in traditional static timing analysis, and if timing is verified, then the desired yield is met. Using process-specific "generic paths" representing critical paths in a given process technology, and requiring minimum process data, our approach can be used early in the design process, pre-placement. Within-die variations are taken care of using a simple model that assumes their positive correlation, which leads to upper and lower bounds on the timing yield. Our approach also handles both setup and hold timing constraints, and is extended as well to include the effect of statistical clock skew fluctuations resulting from process variations. The end result is a process-specific statistical static timing analysis tool that can be applied either to predict yield, or help in designing chips that meet a specific yield target.