The past decade of logic synthesis research has looked at using Binary Decision Diagrams (BDDs) as an alternative to the traditional sum-of-product representation of logic functions. When compared to the later, logic synthesis algorithms using BDDs have been shown to have significantly better scalability, however, the area quality produced has been poor. This thesis describes two new improvements to BDD-based logic synthesis. The first is a sharing extraction algorithm to improve area. The second is a logic folding approach, where equivalent logic transformations are shared to improve runtime.The algorithms are evaluated in a new logic synthesis tool called FBDD. Experimental results on the MCNC benchmarks show an average area savings of 21% and runtime improvements of 3 times, when compared to a state-of-the-art BDD based logic synthesis system.