An edition of SystemVerilog for design
(2003)
SystemVerilog For Design
A Guide to Using SystemVerilog for Hardware Design and Modeling
1 edition
by Sutherland, Stuart., Stuart Sutherland, Simon Davidmann, and Peter Flake
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Subjects
Computer simulation, Design and construction, Electronic digital computers, Verilog (Computer hardware description language), Computer Hardware & Operating Systems, Electronics engineering, Systems analysis & design, Engineering - Electrical & Electronic, Computer Books: Languages, Computers, Technology & Industrial Arts, Programming - Systems Analysis & Design, CAD-CAM - General, Electronics - Circuits - General, Technology / Electronics / Circuits / General, Programming Languages - General| Edition | Availability |
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1
SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling
2004, Kluwer
in English
1402075308 9781402075308
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2
SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling
June 30, 2003, Springer
Hardcover
in English
- 1 edition
1402075308 9781402075308
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Book Details
First Sentence
"System Verilog is a standard set of extensions to the IEEE Std."
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- Created April 29, 2008
- 4 revisions
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| July 31, 2019 | Edited by MARC Bot | associate edition with work OL5748217W |
| April 14, 2010 | Edited by Open Library Bot | Linked existing covers to the edition. |
| September 1, 2008 | Edited by RenameBot | fix author name |
| April 29, 2008 | Created by an anonymous user | Imported from amazon.com record |