An edition of SystemVerilog for Verification
(2006)
SystemVerilog for Verification
A Guide to Learning the Testbench Language Features
3rd ed. 2012.
by Chris Spear
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Subjects
Systems engineering, Circuits and Systems, Computer input-output equipment, Computers, Engineering, Computer-Aided Engineering (CAD, CAE) and Design, Computer engineering, Computer-aided design, Electrical engineering, Verification, Integrated circuits, SystemVerilog (Computer hardware description language), Verilog (computer hardware description language), Object-oriented programming (computer science), Computer hardware description languages, Object-oriented programming (Computer science), Ingénierie| Edition | Availability |
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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
Feb 14, 2012, Springer
paperback
1461407168 9781461407164
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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
2012, Springer US
electronic resource :
in English
- 3rd ed. 2012.
146140715X 9781461407157
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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
2012, Springer
in English
1461407141 9781461407140
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zzzz
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SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
2006, Springer
in English
0387270388 9780387270388
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zzzz
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Book Details
Table of Contents
1. Verification Guidelines
1.1. The Verification Process
1.1.1. Testing at Different Levels
1.1.2. The Verification Plan
1.2. The Verification Methodology Manual
1.3. Basic Testbench Functionality
1.4. Directed Testing
1.5. Methodology Basics
1.6. Constrained-Random Stimulus
1.7. What Should You Randomize?
1.7.1. Device and Environment Configuration
1.7.2. Input Data
1.7.3. Protocol Exceptions, Errors, and Violations
1.7.4. Delays and Synchronization
1.7.5. Parallel Random Testing
1.8. Functional Coverage
1.8.1. Feedback from Functional Coverage to Stimulus
1.9. Testbench Components
1.10. Layered Testbench
1.10.1. A Flat Testbench
1.10.2. The Signal and Command Layers
1.10.3. The Functional Layer
1.10.4. The Scenario Layer
1.10.5. The Test Layer and Functional Coverage
1.11. Building a Layered Testbench
1.11.1. Creating a Simple Driver
1.12. Simulation Environment Phases
1.13. Maximum Code Reuse
1.14. Testbench Performance
1.15. Conclusion
1.16. Exercises
2. Data Types
2.1. Built-In Data Types
2.1.1. The Logic Type
2.1.2. 2-State Data Types
2.2. Fixed-Size Arrays
2.2.1. Declaring and Initializing Fixed-Size Arrays
2.2.2. The Array Literal
2.2.3. Basic Array Operations - for and foreach
2.2.4. Basic Array Operations - Copy and Compare
2.2.5. Bit and Array Subscripts, Together at Last
2.2.6. Packed Arrays
2.2.7. Packed Array Examples
2.2.8. Choosing Between Packed and Unpacked Arrays
2.3. Dynamic Arrays
2.4. Queues
2.5. Associative Arrays
2.6. Array Methods
2.6.1. Array Reduction Methods
2.6.2. Array Locator Methods
2.6.3. Array Sorting and Ordering
2.6.4. Building a Scoreboard with Array Locator Methods
2.7. Choosing a Storage Type
2.7.1. Flexibility
2.7.2. Memory Usage
2.7.3. Speed
2.7.4. Data Access
2.7.5. Choosing the Best Data Structure
2.8. Creating New Types with typedef
2.9. Creating User-Defined Structures
2.9.1. Creating a Struct and a New Type
2.9.2. Initializing a Structure
2.9.3. Making a Union of Several Types
2.9.4. Packed Structures
2.9.5. Choosing Between Packed and Unpacked Structures
2.10. Packages
2.11. Type Conversion
2.11.1. The Static Cast
2.11.2. The Dynamic Cast
2.12. Streaming Operators
2.13. Enumerated Types
2.13.1. Defining Enumerated Values
2.13.2. Routines for Enumerated Types
2.13.3. Converting To and From Enumerated Types
2.14. Constants
2.15. Strings
2.16. Expression Width
2.17. Conclusion
2.18. Exercises
3. Procedural Statements and Routines
3.1. Procedural Statements
3.2. Tasks, Functions, and Void Functions
3.3. Routine Overview
3.3.1. Routine Begin ... End Removed
3.4. Routine Arguments
3.4.1. C-style Routine Arguments
3.4.2. Argument Direction
3.4.3. Advanced Argument Types
3.4.4. Default Value for an Argument
3.4.5. Passing Arguments by Name
3.4.6. Common Coding Errors
3.5. Returning from a Routine
3.5.1. The Return Statement
3.5.2. Returning an Array from a Function
3.6. Local Data Storage
3.6.1. Automatic Storage
3.6.2. Variable Initialization
3.7. Time Values
3.7.1. Time Units and Precision
3.7.2. Time Literals
3.7.3. Time and Variables
3.7.4. $time vs. $realtime
3.8. Conclusion
3.9. Exercises
4. Connecting the Testbench and Design
4.1. Separating the Testbench and Design
4.1.1. Communication Between the Testbench and the DUT
4.1.2. Communication with Ports
4.2. The Interface Construct
4.2.1. Using an Interface to Simplify Connections
4.2.2. Connecting Interfaces and Ports
4.2.3. Grouping Signals in an Interface Using Modports
4.2.4. Using Modports with a Bus Design
4.2.5. Creating an Interface Monitor
4.2.6. Interface Trade-Offs
4.2.7. More Information and Examples
4.2.8. Logic vs. Wire in an Interface
4.3. Stimulus Timing
4.3.1. Controlling Timing of Synchronous Signals with a Clocking Block
4.3.2. Timing Problems in Verilog
4.3.3. Testbench-Design Race Condition
4.3.4. The Program Block and Timing Regions
4.3.5. Specifying Delays Between the Design and Testbench
4.4. Interface Driving and Sampling
4.4.1. Interface Synchronization
4.4.2. Interface Signal Sample
4.4.3. Interface Signal Drive
4.4.4. Driving Interface Signals Through a Clocking Block
4.4.5. Bidirectional Signals in the Interface
4.4.6. Specifying Delays in Clocking Blocks
4.5. Program Block Considerations
4.5.1. The End of Simulation
4.5.2. Why Are Always Blocks Not Allowed in a Program?
4.5.3. The Clock Generator
4.6. Connecting It All Together
4.6.1. An Interface in a Port List Must Be Connected
4.7. Top-Level Scope
4.8. Program-Module Interactions
4.9. SystemVerilog Assertions
4.9.1. Immediate Assertions
4.9.2. Customizing the Assertion Actions
4.9.3. Concurrent Assertions
4.9.4. Exploring Assertions
4.10. The Four-Port ATM Router
4.10.1. ATM Router with Ports
4.10.2. ATM Top Level Module with Ports
4.10.3. Using Interfaces to Simplify Connections
4.10.4. ATM Interfaces
4.10.5. ATM Router Model Using an Interface
4.10.6. ATM Top-Level Module with Interfaces
4.10.7. ATM Testbench with Interface
4.11. The Ref Port Direction
4.12. Conclusion
4.13. Exercises
5. Basic OOP
5.1. Introduction
5.2. Think of Nouns, Not Verbs
5.3. Your First Class
5.4. Where to Define a Class
5.5. OOP Terminology
5.6. Creating New Objects
5.6.1. Handles and Constructing Objects
5.6.2. Custom Constructor
5.6.3. Separating the Declaration and Construction
5.6.4. The Difference Between new() and new[]
5.6.5. Getting a Handle on Objects
5.7. Object Deallocation
5.8. Using Objects
5.9. Class Methods
5.10. Defining Methods Outside of the Class
5.11. Static Variables vs. Global Variables
5.11.1. A Simple Static Variable
5.11.2. Accessing Static Variables Through the Class Name
5.11.3. Initializing Static Variables
5.11.4. Static Methods
5.12. Scoping Rules
5.12.1. What Is This?
5.13. Using One Class Inside Another
5.13.1. How Big or Small Should My Class Be?
5.13.2. Compilation Order Issue
5.14. Understanding Dynamic Objects
5.14.1. Passing Objects and Handles to Methods
5.14.2. Modifying a Handle in a Task
5.14.3. Modifying Objects in Flight
5.14.4. Arrays of Handles
5.15. Copying Objects
5.15.1. Copying an Object with the new Operator
5.15.2. Writing Your Own Simple Copy Function
5.15.3. Writing a Deep Copy Function
5.15.4. Packing Objects to and from Arrays Using Streaming Operators
5.16. Public vs. Local
5.17. Straying Off Course
5.18. Building a Testbench
5.19. Conclusion
5.20. Exercises
6. Randomization
6.1. Introduction
6.2. What to Randomize
6.2.1. Device Configuration
6.2.2. Environment Configuration
6.2.3. Primary Input Data
6.2.4. Encapsulated Input Data
6.2.5. Protocol Exceptions, Errors, and Violations
6.2.6. Delays
6.3. Randomization in SystemVerilog
6.3.1. Simple Class with Random Variables
6.3.2. Checking the Result from Randomization
6.3.3. The Constraint Solver
6.3.4. What Can Be Randomized?
6.4. Constraint Details
6.4.1. Constraint Introduction
6.4.2. Simple Expressions
6.4.3. Equivalence Expressions
6.4.4. Weighted Distributions
6.4.5. Set Membership and the inside Operator
6.4.6. Using an Array in a Set
6.4.7. Bidirectional Constraints
6.4.8. Implication Constraints
6.4.9. Equivalence Operator
6.5. Solution Probabilities
6.5.1. Unconstrained
6.5.2. Implication
6.5.3. Implication and Bidirectional Constraints
6.5.4. Guiding Distribution with solve ... before
6.6. Controlling Multiple Constraint Blocks
6.7. Valid Constraints
6.8. In-Line Constraints
6.9. The pre_randomize and post_randomize Functions
6.9.1. Building a Bathtub Distribution
6.9.2. Note on Void Functions
6.10. Random Number Functions
6.11. Constraints Tips and Techniques
6.11.1. Constraints with Variables
6.11.2. Using Nonrandom Values
6.11.3. Checking Values Using Constraints
6.11.4. Randomizing Individual Variables
6.11.5. Turn Constraints Off and On
6.11.6. Specifying a Constraint in a Test Using In-Line Constraints
6.11.7. Specifying a Constraint in a Test with External Constraints
6.11.8. Extending a Class
6.12. Common Randomization Problems
6.12.1. Use Signed Variables with Care
6.12.2. Solver Performance Tips
6.12.3. Choose the Right Arithmetic Operator to Boost Efficiency
6.13. Iterative and Array Constraints
6.13.1. Array Size
6.13.2. Sum of Elements
6.13.3. Issues with Array Constraints
6.13.4. Constraining Individual Array and Queue Elements
6.13.5. Generating an Array of Unique Values
6.13.6. Randomizing an Array of Handles
6.14. Atomic Stimulus Generation vs. Scenario Generation
6.14.1. An Atomic Generator with History
6.14.2. Random Array of Objects
6.14.3. Combining Sequences
6.14.4. Randsequence
6.15. Random Control
6.15.1. Introduction to randcase
6.15.2. Building a Decision Tree with randcase
6.16. Random Number Generators
6.16.1. Pseudorandom Number Generators
6.16.2. Random Stability - Multiple Generators
6.16.3. Random Stability and Hierarchical Seeding
6.17. Random Device Configuration
6.18. Conclusion
6.19. Exercises
7. Threads and Interprocess Communication
7.1. Working with Threads
7.1.1. Using fork ... join and begin ... end
7.1.2. Spawning Threads with fork ... join none
7.1.3. Synchronizing Threads with fork ... join any
7.1.4. Creating Threads in a Class
7.1.5. Dynamic Threads
7.1.6. Automatic Variables in Threads
7.1.7. Waiting for All Spawned Threads
7.1.8. Sharing Variables Across Threads
7.2. Disabling Threads
7.2.1. Disabling a Single Thread
7.2.2. Disabling Multiple Threads
7.2.3. Disable a Task that Was Called Multiple Times
7.3. Interprocess Communication
7.4. Events
7.4.1. Blocking on the Edge of an Event
7.4.2. Waiting for an Event Trigger
7.4.3. Using Events in a Loop
7.4.4. Passing Events
7.4.5. Waiting for Multiple Events
7.5. Semaphores
7.5.1. Semaphore Operations
7.5.2. Semaphores with Multiple Keys
7.6. Mailboxes
7.6.1. Mailbox in a Testbench
7.6.2. Bounded Mailboxes
7.6.3. Unsynchronized Threads Communicating with a Mailbox
7.6.4. Synchronized Threads Using a Bounded Mailbox and a Peek
7.6.5. Synchronized Threads Using a Mailbox and Event
7.6.6. Synchronized Threads Using Two Mailboxes
7.6.7. Other Synchronization Techniques
7.7. Building a Testbench with Threads and IPC
7.7.1. Basic Transactor
7.7.2. Configuration Class
7.7.3. Environment Class
7.7.4. Test Program
7.8. Conclusion
7.9. Exercises
8. Advanced OOP and Testbench Guidelines
8.1. Introduction to Inheritance
8.1.1. Basic Transaction
8.1.2. Extending the Transaction Class
8.1.3. More OOP Terminology
8.1.4. Constructors in Extended Classes
8.1.5. Driver Class
8.1.6. Simple Generator Class
8.2. Blueprint Pattern
8.2.1. The Environment Class
8.2.2. A Simple Testbench
8.2.3. Using the Extended Transaction Class
8.2.4. Changing Random Constraints with an Extended Class
8.3. Downcasting and Virtual Methods
8.3.1. Downcasting with $cast
8.3.2. Virtual Methods
8.3.3. Signatures and Polymorphism
8.3.4. Constructors are Never Virtual
8.4. Composition, Inheritance, and Alternatives
8.4.1. Deciding Between Composition and Inheritance
8.4.2. Problems with Composition
8.4.3. Problems with Inheritance
8.4.4. A Real-World Alternative
8.5. Copying an Object
8.5.1. Specifying a Destination for Copy
8.6. Abstract Classes and Pure Virtual Methods
8.7. Callbacks
8.7.1. Creating a Callback
8.7.2. Using a Callback to Inject Disturbances
8.7.3. A Quick Introduction to Scoreboards
8.7.4. Connecting to the Scoreboard with a Callback
8.7.5. Using a Callback to Debug a Transactor
8.8. Parameterized Classes
8.8.1. A Simple Stack
8.8.2. Sharing Parameterized Classes
8.8.3. Parameterized Class Suggestions
8.9. Static and Singleton Classes
8.9.1. Dynamic Class to Print Messages
8.9.2. Singleton Class to Print Messages
8.9.3. Configuration Database with Static Parameterized Class
8.10. Creating a Test Registry
8.10.1. Test Registry with Static Methods
8.10.2. Test Registry with a Proxy Class
8.10.3. UVM Factory Build
8.11. Conclusion
8.12. Exercises
9. Functional Coverage
9.1. Gathering Coverage Data
9.2. Coverage Types
9.2.1. Code Coverage
9.2.2. Functional Coverage
9.2.3. Bug Rate
9.2.4. Assertion Coverage
9.3. Functional Coverage Strategies
9.3.1. Gather Information, Not Data
9.3.2. Only Measure What You Are Going to Use
9.3.3. Measuring Completeness
9.4. Simple Functional Coverage Example
9.5. Anatomy of a Cover Group
9.5.1. Defining a Cover Group in a Class
9.6. Triggering a Cover Group
9.6.1. Sampling Using a Callback
9.6.2. Cover Group with a User-Defined Sample Argument List
9.6.3. Cover Group with an Event Trigger
9.6.4. Triggering on a SystemVerilog Assertion
9.7. Data Sampling
9.7.1. Individual Bins and Total Coverage
9.7.2. Creating Bins Automatically
9.7.3. Limiting the Number of Automatic Bins Created
9.7.4. Sampling Expressions
9.7.5. User-Defined Bins Find a Bug
9.7.6. Naming the Cover Point Bins
9.7.7. Conditional Coverage
9.7.8. Creating Bins for Enumerated Types
9.7.9. Transition Coverage
9.7.10. Wildcard States and Transitions
9.7.11. Ignoring Values
9.7.12. Illegal Bins
9.7.13. State Machine Coverage
9.8. Cross Coverage
9.8.1. Basic Cross Coverage Example
9.8.2. Labeling Cross Coverage Bins
9.8.3. Excluding Cross Coverage Bins
9.8.4. Excluding Cover Points from the Total Coverage Metric
9.8.5. Merging Data from Multiple Domains
9.8.6. Cross Coverage Alternatives
9.9. Generic Cover Groups
9.9.1. Pass Cover Group Arguments by Value
9.9.2. Pass Cover Group Arguments by Reference
9.10. Coverage Options
9.10.1. Per-Instance Coverage
9.10.2. Cover Group Comment
9.10.3. Coverage Threshold
9.10.4. Printing the Empty Bins
9.10.5. Coverage Goal
9.11. Analyzing Coverage Data
9.12. Measuring Coverage Statistics During Simulation
9.13. Conclusion
9.14. Exercises
10. Advanced Interfaces
10.1. Virtual Interfaces with the ATM Router
10.1.1. The Testbench with Just Physical Interfaces
10.1.2. Testbench with Virtual Interfaces
10.1.3. Connecting the Testbench to an Interface in a Port List
10.1.4. Connecting the Test to an Interface with an XMR
10.2. Connecting to Multiple Design Configurations
10.2.1. A Mesh Design
10.2.2. Using Typedefs with Virtual Interfaces
10.2.3. Passing Virtual Interface Array Using a Port
10.3. Parameterized Interfaces and Virtual Interfaces
10.4. Procedural Code in an Interface
10.4.1. Interface with Parallel Protocol
10.4.2. Interface with Serial Protocol
10.4.3. Limitations of Interface Code
10.5. Conclusion
10.6. Exercises
11. A Complete SystemVerilog Testbench
11.1. Design Blocks
11.2. Testbench Blocks
11.3. Alternate Tests
11.3.1. Your First Test - Just One Cell
11.3.2. Randomly Drop Cells
11.4. Conclusion
11.5. Exercises
12. Interfacing with C/C++
12.1. Passing Simple Values
12.1.1. Passing Integer and Real Values
12.1.2. The import Declaration
12.1.3. Argument Directions
12.1.4. Argument Types
12.1.5. Importing a Math Library Routine
12.2. Connecting to a Simple C Routine
12.2.1. A Counter with Static Storage
12.2.2. The chandle Data Type
12.2.3. Representation of Packed Values
12.2.4. 4-State Values
12.2.5. Converting from 2-State to 4-State
12.3. Connecting to C++
12.3.1. The Counter in C++
12.3.2. Static Methods
12.3.3. Communicating with a Transaction-Level C++ Model
12.4. Simple Array Sharing
12.4.1. Single-Dimension Arrays - 2-State
12.4.2. Single-Dimension Arrays - 4-State
12.5. Open Arrays
12.5.1. Basic Open Array
12.5.2. Open Array Methods
12.5.3. Passing Unsized Open Arrays
12.5.4. Packed Open Arrays in DPI
12.6. Sharing Composite Types
12.6.1. Passing Structures Between SystemVerilog and C
12.6.2. Passing Strings Between SystemVerilog and C
12.7. Pure and Context Imported Methods
12.8. Communicating from C to SystemVerilog
12.8.1. A Simple Exported Function
12.8.2. C Function Calling a SystemVerilog Function
12.8.3. C Task Calling a SystemVerilog Task
12.8.4. Calling Methods in Objects
12.8.5. The Meaning of Context
12.8.6. Setting the Scope for an Imported Routine
12.9. Connecting Other Languages
12.10. Conclusion
12.11. Exercises
References
Index
Edition Notes
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