An edition of Hardware and Software: Verification and Testing
(2012)
Hardware and Software: Verification and Testing
7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers
by Kerstin Eder
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This book constitutes the thoroughly refereed post-conference proceedings of the 7th International Haifa Verification Conference, HVC 2011, held in Haifa, Israel in December 2011.
The 15 revised full papers presented together with 3 tool papers and 4 posters were carefully reviewed and selected from 43 submissions. The papers are organized in topical sections on synthesis, formal verification, software quality, testing and coverage, experience and tools, and posters- student event.
Publish Date
2012
Publisher
Springer Berlin Heidelberg,
Imprint: Springer
Language
English
Pages
263
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Subjects
Logic design, Logics and Meanings of Programs, Computer science, Software engineering, Programming Languages, Compilers, Interpreters, Artificial intelligence, Artificial Intelligence (incl. Robotics), Computer programs, Congresses, Verification, Software architecture, Computer software, testing, Computer input-output equipment| Edition | Availability |
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Hardware and Software: Verification and Testing: 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised Selected Papers
2012, Springer Berlin Heidelberg, Imprint: Springer
electronic resource :
in English
3642341888 9783642341885
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Hardware and Software : Verification and Testing: 7th International Haifa Verification Conference, HVC 2011, Haifa, Israel, December 6-8, 2011, Revised ...
Oct 09, 2012, Springer
paperback
364234187X 9783642341878
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Book Details
Table of Contents
<p>Preprocessing and Inprocessing Techniques in SAT<i>
</i>ioneering the Future of Verification: A Spiral of Technological and Business Innovation
Automated Detection and Repair of Concurrency Bugs
Verification Challenges of Workload Optimized Hardware Systems
Synthesis with Clairvoyance
Generalized Reactivity(1) Synthesis without a Monolithic Strategy
IIS-Guided DFS for Efficient Bounded Reachability Analysis of Linear Hybrid Automata
Cube and Conquer: Guiding CDCL SAT Solvers by Lookaheads.Implicative Simultaneous Satisfiability and Applications
Liveness vs Safety – A Practical Viewpoint
Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search
SAM: Self-adaptive Dynamic Analysis for Multithreaded Programs
Concurrent Small Progress Measures
Specification and Quantitative Analysis of Probabilistic Cloud Deployment Patterns
Interpolation-Based Function Summaries in Bounded Model Checking
^
Can File Level Characteristics Help Identify System Level Fault-Proneness
Reverse Coverage Analysis
Symbolic Testing of OpenCL Code
Dynamic Test Data Generation for Data Intensive Applications
Injecting Floating-Point Testing Knowledge into Test Generators
Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE
HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware
On-Line Detection and Prediction of Temporal Patterns
Function Summaries in Software Upgrade Checking
The Rabin Index of Parity Games
Using Computational Biology Methods to Improve Post-silicon Microprocessor Testing. </p><i>
</i>ioneering the Future of Verification: A Spiral of Technological and Business Innovation
Automated Detection and Repair of Concurrency Bugs
Verification Challenges of Workload Optimized Hardware Systems
Synthesis with Clairvoyance
Generalized Reactivity(1) Synthesis without a Monolithic Strategy
^
^^
IIS-Guided DFS for Efficient Bounded Reachability Analysis of Linear Hybrid Automata
Cube and Conquer: Guiding CDCL SAT Solvers by Lookaheads.Implicative Simultaneous Satisfiability and Applications
Liveness vs Safety – A Practical Viewpoint
Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search
SAM: Self-adaptive Dynamic Analysis for Multithreaded Programs
Concurrent Small Progress Measures
Specification and Quantitative Analysis of Probabilistic Cloud Deployment Patterns
Interpolation-Based Function Summaries in Bounded Model Checking
Can File Level Characteristics Help Identify System Level Fault-Proneness
Reverse Coverage Analysis
Symbolic Testing of OpenCL Code
Dynamic Test Data Generation for Data Intensive Applications
Injecting Floating-Point Testing Knowledge into Test Generators
Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE
^
^^
HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware
On-Line Detection and Prediction of Temporal Patterns
Function Summaries in Software Upgrade Checking
The Rabin Index of Parity Games
Using Computational Biology Methods to Improve Post-silicon Microprocessor Testing.
^^
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- Created July 1, 2019
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| March 28, 2025 | Edited by ImportBot | Redacting ocaids |
| December 14, 2022 | Edited by MARC Bot | import existing book |
| February 27, 2022 | Edited by ImportBot | import existing book |
| November 13, 2020 | Edited by MARC Bot | import existing book |
| July 1, 2019 | Created by MARC Bot | Imported from Internet Archive item record |