An edition of Logic design and verification using SystemVerilog : (revised) (2016)

Logic design and verification using SystemVerilog : (revised)

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Cover of: Logic design and verification using SystemVerilog : (revised) by D. E. Thomas
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Last edited by ImportBot
October 3, 2024 | History
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An edition of Logic design and verification using SystemVerilog : (revised) (2016)

Logic design and verification using SystemVerilog : (revised)

by

  • 6 Want to read

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Publish Date
Publisher
CreateSpace, CreateSpace Independent Publishing Platform, Createspace Independent Publishing Platform
Pages
336

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Subjects

SystemVerilog (Computer hardware description language), Electronic circuits, Computer hardware description languages
Edition Availability
Cover of: Logic design and verification using SystemVerilog : (revised)
Logic design and verification using SystemVerilog : (revised)
2016, CreateSpace, CreateSpace Independent Publishing Platform, Createspace Independent Publishing Platform

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Book Details

Classifications

Library of Congress
TK7885.7 .T478 2016, TK7885.7.T4 2016

Edition Identifiers

Open Library
OL27012978M
ISBN 13
9781523364022
OCLC/WorldCat
959835598

Work Identifiers

Work ID
OL19822255W

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History

Download catalog record: RDF / JSON / OPDS | Wikipedia citation
October 3, 2024 Edited by ImportBot import existing book
December 20, 2023 Edited by ImportBot import existing book
February 11, 2023 Edited by ImportBot import existing book
December 19, 2022 Edited by MARC Bot import existing book
June 26, 2019 Created by Marco Galdos Added new book.