An edition of Digital logic simulation and CPLD programming with VHDL
(2003)
Digital logic simulation and CPLD programming with VHDL
by Steve Waterman
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Previews available in: English
| Edition | Availability |
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1
Digital logic simulation and CPLD programming with VHDL
2003, Prentice Hall
in English
0130967602 9780130967602
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Book Details
Table of Contents
Section 1 : Asynchronous circuits
logic gates ; Boolean laws, principles, and rules ; Combinational logic circuits ; Implementing logic designs ; Implementing logic designs with VHDL ; Adders ; Adding and subtracting ; Comparators ; Parity ; Encoders ; Decoders ; Multiplexers ; Demultiplexers ; Latches ; 555 timer
Section 2 : Synchronous circuits
Flip-flops ; Asynchronous counters ; Synchronous counters ; Shift registers
Section 3 : Library of paramatize modules (LPM functions)
LPMA̲nd ; LPMA̲dd ; LPMC̲ompare ; LPMD̲ecode ; LPMM̲UX ; LPMC̲OUNTER ; LMPS̲HIFTREG
Section 4 : Appendices.
Edition Notes
Includes bibliographical references (p. 297).
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- Created August 10, 2011
- 6 revisions
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| November 17, 2022 | Edited by ImportBot | import existing book |
| December 5, 2020 | Edited by MARC Bot | import existing book |
| August 19, 2020 | Edited by ImportBot | import existing book |
| July 22, 2019 | Edited by MARC Bot | remove fake subjects |
| August 10, 2011 | Created by ImportBot | Imported from Internet Archive item record |