The Reduced Instruction Set Computer (RISC) concept is an important new way of optimizing computer architecture. This book demonstrates that the recent trend in computer architecture toward the use of increasingly complex instruction sets leads to the inefficient use of hardware resources. In the area of VLSI, especially, the wiring and gate delays, and the limitations in total transistor count and in power dissipation, typically mean that extra "features" added to speed up some of the function of the computer will slow down the other operations. Reduced Instruction Set Computer architectures offer an alternative by allowing for the effective use of on-chip transistors in the functional units that provide fast access to frequently use operands and instructions. This book describes the design and implementation of the RISC II single-chip processor which incorporates a very simple instruction set and multiple overlapping register-windows, thus achieving surprisingly high performance at surprisingly low cost.

Manolis G.H. Katevenis received his doctorate from the University of California, Berkeley. H is currently Assistant Professor of Computer Science at Stanford University.

Reduced Instruction Set Computer Architectures for VLSI is the third book in the ACM Doctoral Dissertation Award Series.