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VLSI for neural networks and artificial intelligence
1994, Springer Science+Business Media
electronic resource /
in English
1489913319 9781489913319
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Book Details
Table of Contents
Analog Circuits for Neural Networks
Analog VLSI Neural Learning Circuits -A Tutorial
An Analog CMOS Implementation of a Kohonen Network with Learning Capability
Back-Propagation Learning Algorithms for Analog VLSI Implementation
An Analog Implementation of the Boltzmann Machine with Programmable Learning Algorithms
A VLSI Design of the Minimum Entropy Neuron
A Multi-Layer Analog VLSI Architecture for Texture Analysis Isomorphic to Cortical Cells in Mammalian Visual System
Digital Implementations of Neural Networks
A VLSI Pipelined Neuroemulator
A Low Latency Digital Neural Network Architecture
MANTRA: A Multi-Model Neural-Network Computer
SPERT: A Neuro-Microprocessor
Design of Neural Self-Organization Chips for Semantic Applications
VLSI Implementation of a Digital Neural Network with Reward-Penalty Learning
Asynchronous VLSI Design for Neural System Implementation
Neural Networks on Multiprocessor Systems and Applications
VLSI-Implementation of Associative Memory Systems for Neural Information Processing
A Dataflow Approach for Neural Networks
A Custom Associative Chip Used as a Building Block for a Software Reconfigurable Multi-Network Simulator
Parallel Implementation of Neural Associative Memories on RISC Processors
Reconfigurable Logic Implementation of Memory-Based Neural Networks: A Case Study of the CMAC Network
A Cascadable VLSI Design for GENET
Parametrised Neural Network Design and Compilation into Hardware
Knowledge Processing in Neural Architecture
Two Methods for Solving Linear Equations Using Neural Networks
VLSI Machines for Artificial Intelligence
Hardware Support for Data Parallelism in Production Systems
SPACE: Symbolic Processing in Associative Computing Elements
PALM: A Logic Programming System on a Highly Parallel Architecture
A Distributed Parallel Associative Processor (DPAP) for the Execution of Logic Programs
Performance Analysis of a Parallel VLSI Architecture for Prolog
A Prolog VLSI System for Real Time Applications
An Extended WAM Based Architecture for OR-Parallel Prolog Execution
Architecture and VLSI Implementation of a Pegasus-II Prolog Processor
Contributors.
Edition Notes
"Proceedings of an International Workshop on Artificial Intelligence and Neural Networks, held September 2-4, 1992, in Oxford, United Kingdom"--Title page verso.
Includes bibliographical references and index.
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