Much of the progress in solid-state microelectronics has come from the continued reduction in size of the transistors that make up integrated circuits (ICs), having dropped by a factor of 10 in the last decade to where minimum device geometries have reached approximately 350 nanometers in mass production. Continued improvements in ICs will require a device technology that can be scaled down to the sub-100 nanometer size regime. There, the quantum mechanical nature of the electron becomes strongly evident, and new design tools are required for a nano-electronic semiconductor technology. The combined scaling and speed advantages of these new devices could portend orders of magnitude increases in the functional performance of future-generation ICs. Quantum device performance is extremely sensitive to small variations in design parameters. Accurate theoretical modeling is therefore required to guide the technology development. Conventional device design tools are based on classical physics, and do not incorporate quantum effects. New design tools are required to explicitly account for the quantum effects that control charge transport at the nanometer scale. To further understand and develop nanoscale device technology, this thesis will model the potential energy function in a quantum dot, a nanostructure in which electrons are quantum-mechanically confined in all three dimensions and which represents the inevitable result of continued downscaling of semiconductor devices.