Field-programmable gate array logic synthesis using Boolean satisfiability.

Field-programmable gate array logic synthesis ...
Andrew C. Ling, Andrew C. Ling
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January 24, 2010 | History

Field-programmable gate array logic synthesis using Boolean satisfiability.

Field-Programmable gate arrays (FPGAs) are reprogrammable logic chips that can be configured to implement various digital circuits. FPGAs are fast replacing custom ASICs in many areas due to their flexibility and fast turn around times for product development. However, these benefits come at a heavy cost of area, speed, and power.The FPGA architecture and technology mapping phase are fundamental in determining the performance of the FPGA. This thesis presents novel tools using Boolean satisfiability (SAT) to aid in both these areas. First, an architecture efficiency evaluation tool is developed. The tool works by reading in a description of the FPGA architecture and rates how flexible that architecture can be in implementing various circuits. Next, a novel technology mapping approach is developed and compared to current methods. This work contrasts with current approaches since it can be applied to almost any FPGA architecture. Finally, a resynthesis algorithm is described which rates the utility of current FPGA technology mappers where it can also be used to discover optimal configurations of common subcircuits to digital design.

Publish Date
Language
English
Pages
64

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Book Details


Edition Notes

Source: Masters Abstracts International, Volume: 44-02, page: 0997.

Thesis (M.A.Sc.)--University of Toronto, 2005.

Electronic version licensed for access by U. of T. users.

GERSTEIN MICROTEXT copy on microfiche (1 microfiche).

The Physical Object

Pagination
64 leaves.
Number of pages
64

Edition Identifiers

Open Library
OL19216896M
ISBN 10
0494072687

Work Identifiers

Work ID
OL12683523W

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January 24, 2010 Edited by WorkBot add more information to works
December 11, 2009 Created by WorkBot add works page