Improving cache locality for thread-level speculation systems.

Improving cache locality for thread-level spe ...
Stanley Lap Chiu Fung, Stanley ...
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January 24, 2010 | History

Improving cache locality for thread-level speculation systems.

With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the performance of an individual program. However, with such speculatively-parallel execution the cache locality once enjoyed by the original uniprocessor execution is significantly disrupted: for TLS execution on a four-processor CMP, we find that the data-cache miss rates are nearly four-times those of the uniprocessor case, even though TLS execution utilizes four private data caches.We break down the TLS cache locality problem into instruction and data cache, execution stages, and parallel access patterns, and propose methods to improve cache locality in each of these areas. We find that for parallel regions across 13 SPECint applications our simple and low-cost techniques reduce data-cache misses by 38.2%, improve performance by 12.8%, and significantly improve scalability---further enhancing the feasibility of TLS as a way to capitalize on future CMPs.

Publish Date
Language
English
Pages
83

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Book Details


Edition Notes

Source: Masters Abstracts International, Volume: 44-02, page: 0989.

Thesis (M.A.Sc.)--University of Toronto, 2005.

Electronic version licensed for access by U. of T. users.

GERSTEIN MICROTEXT copy on microfiche (1 microfiche).

The Physical Object

Pagination
83 leaves.
Number of pages
83

Edition Identifiers

Open Library
OL19216851M
ISBN 10
0494072598

Work Identifiers

Work ID
OL12683498W

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