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Last edited by WorkBot
January 24, 2010 | History

Improving cache locality for thread-level speculation systems 1 edition

Improving cache locality for thread-level speculation systems
Stanley Lap Chiu Fung

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Improving cache locality for thread-level speculation systems.

Published 2005 .
Written in English.

About the Book

With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the performance of an individual program. However, with such speculatively-parallel execution the cache locality once enjoyed by the original uniprocessor execution is significantly disrupted: for TLS execution on a four-processor CMP, we find that the data-cache miss rates are nearly four-times those of the uniprocessor case, even though TLS execution utilizes four private data caches.We break down the TLS cache locality problem into instruction and data cache, execution stages, and parallel access patterns, and propose methods to improve cache locality in each of these areas. We find that for parallel regions across 13 SPECint applications our simple and low-cost techniques reduce data-cache misses by 38.2%, improve performance by 12.8%, and significantly improve scalability---further enhancing the feasibility of TLS as a way to capitalize on future CMPs.

Edition Notes

Source: Masters Abstracts International, Volume: 44-02, page: 0989.

Thesis (M.A.Sc.)--University of Toronto, 2005.

Electronic version licensed for access by U. of T. users.

GERSTEIN MICROTEXT copy on microfiche (1 microfiche).

The Physical Object

Pagination
83 leaves.
Number of pages
83

ID Numbers

Open Library
OL19216851M
ISBN 10
0494072598

History

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January 24, 2010 Edited by WorkBot add more information to works
December 11, 2009 Created by WorkBot add works page