As VLSI designs grow in complexity and size, errors introduced during the design flow become more frequent, complex, and difficult to track. Debugging is the process of locating the source(s) of the error and applying corrections to rectify the design. Although much advancement has been made in the field of verification, debugging remains a manual and a resource-intensive step that consumes up to 60% of the design time and cost. This thesis proposes two novel debugging techniques, the first tackles flat gate-level sequential circuits, while the second handles hierarchical designs. The algorithms are based on Boolean Satisfiability (SAT) and Quantified Boolean Formula (QBF) Satisfiability, which are two fields that have experienced rapid development over the past few years due to their many applications in Electronic Design Automation (EDA). Experimental evaluation demonstrates that the proposed techniques are effective in reducing run-time and memory-requirements.