The Multi-Level Computing Architecture (MLCA) is a novel architecture for parallel systems-on-a-chip. We propose and evaluate a profile-driven compiler technique for power optimizations of MLCA applications using dynamic voltage scaling (DVS). Our technique combines dependence analysis of loops with profiling in order to identify the slack in parallel execution of coarse-grain tasks. DVS is applied to slow down processors executing tasks outside the critical path, saving power with little or no impact on execution time. Evaluation of our technique using an MLCA simulator and three realistic MLCA multimedia applications shows that up to 10% savings in processor power consumption can be achieved with no more than 1.5% increase in execution time. The achieved power savings are significantly greater than those that could be achieved by uniformly slowing down all computations with only a similar increase in overall execution time.