Towards a compilation infrastructure for network processors.

Towards a compilation infrastructure for netw ...
Martin Labrecque, Martin Labre ...
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January 24, 2010 | History

Towards a compilation infrastructure for network processors.

Modern network processors (NPs) typically resemble a highly-multithreaded multiprocessor-on-a-chip, supporting a wide variety of mechanisms for on-chip storage and inter-task communication. NP applications are themselves composed of many threads that share memory and other resources, and synchronize and communicate frequently. In contrast, studies of new NP architectures and features are often performed by benchmarking a simulation model of the new NP using independent kernel programs that neither communicate nor share memory. In this paper we present a NP simulation infrastructure that (i) uses realistic NP applications that are multithreaded, share memory, synchronize, and communicate; and (ii) automatically maps these applications to a variety of NP architectures and features. We use our infrastructure to evaluate threading and scaling, on-chip storage and communication, and to suggest future techniques for automated compilation for NPs.

Publish Date
Language
English
Pages
132

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Book Details


Edition Notes

Source: Masters Abstracts International, Volume: 44-06, page: 2920.

Thesis (M.A.Sc.)--University of Toronto, 2006.

Electronic version licensed for access by U. of T. users.

ROBARTS MICROTEXT copy on microfiche.

The Physical Object

Pagination
132 leaves.
Number of pages
132

Edition Identifiers

Open Library
OL19215643M
ISBN 13
9780494163375

Work Identifiers

Work ID
OL12682896W

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