The CMOS sensory image processor presented here performs spatially-oversampling computational image quantization directly on the focal plane. A bank of column-parallel first-order incremental DeltaSigma-modulated analog-to-digital converters (ADCs) performs column-wise distributed focal-plane oversampling of up to eight adjacent pixels and concurrent weighted average quantization. Number of samples per pixel and switched capacitor sampling sequence order set the amplitude and sign of the respective pixel coefficient. A simple digital delay and adder loop performs spatial accumulation over up to eight adjacent ADC outputs during readout. This amounts to computing a two-dimensional block matrix transform with up to 8x8-pixel programmable kernel in parallel for all columns. A 128x128 active pixel array integrated with a bank of 128 algorithmic DeltaSigma-modulated analog-to-digital converters was fabricated in a 0.35 mum CMOS technology. The 3.1 mm x 1.9 mm prototype, ViPro, captures 8-bit digital video at 30 frames per second and yields up to 4 GMACS projected computational throughput in applications of real-time video compression and visual pattern recognition when scaled to HDTV 1080i resolution.