Formal VLSI correctness verification

proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design

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Last edited by MARC Bot
July 30, 2024 | History

Formal VLSI correctness verification

proceedings of the IFIP WG 10.2/WG 10.5 International Workshop on Applied Formal Methods for Correct VLSI Design

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Previews available in: English

Book Details


Edition Notes

Includes bibliographical references.

Published in
Amsterdam, New York, New York, N.Y
Series
VLSI design methods ;, 2
Genre
Congresses.

Classifications

Dewey Decimal Class
621.39/5
Library of Congress
TK7874 .I3283 1989a

The Physical Object

Pagination
xv, 427 p. :
Number of pages
427

Edition Identifiers

Open Library
OL1855134M
Internet Archive
formalvlsicorrec0000ifip
ISBN 10
0444886885
LCCN
90006949
OCLC/WorldCat
21195272
Goodreads
3583937

Work Identifiers

Work ID
OL4445331W

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