An edition of Proceedings
(1997)
Proceedings
International Workshop on Memory Technology, Design, and Testing
by IEEE International Workshop on Memory Te...
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Last edited by Open Library Bot
April 13, 2010 | History
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1
International Workshop on Memory Technology, Design and Testing: Proceedings
July 1997, Institute of Electrical & Electronics Enginee
Paperback
in English
0818680997 9780818680991
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2
Proceedings: International Workshop on Memory Technology, Design, and Testing
1997, IEEE Computer Society Press
in English
0818680997 9780818680991
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3
Proceedings: International Workshop on Memory Technology, Design, and Testing
1997, IEEE Computer Society Press
Unknown Binding
in English
0818681004 9780818681004
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Book Details
Table of Contents
Matching memory to the power of personal computers / R. Foss
A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.]
High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.]
An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev
SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen
False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley
A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker
Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant
A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao
A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.]
Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang
An open notation for memory tests / A. Offerman, A. van de Goor
Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.]
Memory array testing through a scannable configuration / S. Yano, N. Ishiura
A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.].
Edition Notes
Includes bibliographical references and index.
"August 11-12, 1997, San Jose, California"--Cover.
"IEEE Order Plan Catalog Number 95TB100159"--T.p. verso.
"IEEE Computer Society Order Number PR08099"--T.p. verso.
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History
- Created April 1, 2008
- 4 revisions
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| April 13, 2010 | Edited by Open Library Bot | Linked existing covers to the edition. |
| April 2, 2010 | Edited by bgimpertBot | Added goodreads ID. |
| December 11, 2009 | Edited by WorkBot | link works |
| April 1, 2008 | Created by an anonymous user | Imported from Scriblio MARC record |