Logic Synthesis for Low Power VLSI Designs

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Last edited by ImportBot
January 31, 2024 | History

Logic Synthesis for Low Power VLSI Designs

Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

Publish Date
Pages
258

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Edition Availability
Cover of: Logic Synthesis for Low Power VLSI Designs
Logic Synthesis for Low Power VLSI Designs
1998, Springer US
electronic resource / in English
Cover of: Logic Synthesis for Low Power VLSI Designs
Logic Synthesis for Low Power VLSI Designs
Nov 30, 1997, Springer My Copy UK
paperback

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Book Details


The Physical Object

Format
paperback
Number of pages
258

Edition Identifiers

Open Library
OL28008936M
ISBN 10
1461554543
ISBN 13
9781461554547

Work Identifiers

Work ID
OL19884551W

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January 31, 2024 Edited by ImportBot import existing book
May 6, 2020 Created by ImportBot Imported from amazon.com record