An edition of VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology (1985)

VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology

by Richard J. Jr Simchik

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May 21, 2020 | History

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An edition of VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology (1985)

VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology

by Richard J. Jr Simchik

0 Ratings
0 Want to read
0 Currently reading
0 Have read

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Publish Date

1985

Language

English

Pages

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Previews available in: English

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1 VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology 1985 in English	aaaa Read Listen

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Book Details

Edition Notes

Available from National Technical Information Service, Springfield, Va.

ADA159433.

Thesis (M.S. in E.E.) Naval Postgraduate School, 1985.

Includes bibliographical references.

c.1 - 215252, c.2 - 215253

The Physical Object

Pagination: 94 p.
Number of pages: 94

ID Numbers

Open Library: OL25503768M
Internet Archive: vlsidesignofsixt00simc

Source records

Internet Archive item record

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Created July 26, 2014
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May 21, 2020	Edited by CoverBot	Added new cover
July 26, 2014	Created by ImportBot	Imported from Internet Archive item record

VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology

by Richard J. Jr Simchik