| Record ID | marc_records_scriblio_net/part17.dat:58528579:1270 |
| Source | Scriblio |
| Download Link | /show-records/marc_records_scriblio_net/part17.dat:58528579:1270?format=raw |
LEADER: 01270cam 2200289 a 4500
001 84015490 //r85
003 DLC
005 19850320000000.0
008 840713s1984 maua b 00100 eng
010 $a 84015490 //r85
020 $a0898381649
050 0 $aTK7868.L6$bL626 1984
082 0 $a621.381/73$219
245 00 $aLogic minimization algorithms for VLSI synthesis /$cby Robert K. Brayton ... [et al.].
260 0 $aBoston :$bKluwer Academic Publishers,$cc1984.
300 $aix, 193 p. :$bill. ;$c25 cm.
490 1 $aThe Kluwer international series in engineering and computer science ;$vSECS 2.$aVLSI, computer architecture, and digital signal processing.
504 $aBibliography: p. [174]-190.
500 $aIncludes index.
650 0 $aLogic design.
650 0 $aIntegrated circuits$xVery large scale integration.
650 0 $aIntegrated circuits$xDesign and construction$xData processing.
650 0 $aAlgorithms.
700 10 $aBrayton, Robert King.
740 01 $aLogic minimization algorithms for V.L.S.I. synthesis.
830 0 $aKluwer international series in engineering and computer science ;$vSECS 2.
830 0 $aKluwer international series in engineering and computer science.$pVLSI, computer architecture, and digital signal processing.