| Record ID | marc_nuls/NULS_PHC_180925.mrc:54354873:1434 |
| Source | marc_nuls |
| Download Link | /show-records/marc_nuls/NULS_PHC_180925.mrc:54354873:1434?format=raw |
LEADER: 01434pam 22003734a 4500
001 9922205900001661
005 20150423142756.0
008 050527s2005 nyua b 001 0 eng
010 $a 2005050148
020 $a0387257381
020 $a0387265287 (e-book)
024 3 $a9780387257389
024 3 $a9780387265285
035 $a(CSdNU)u261602-01national_inst
035 $a(OCoLC)60558681
040 $aDLC$cDLC$dC#P$dBAKER
042 $apcc
049 $aCNUM
050 00 $aTK7874.75$b.S72 2005
082 00 $a621.39/5$222
100 1 $aSrivastava, Ashish.
245 10 $aStatistical analysis and optimization for VLSI :$btiming and power / $cAshish Srivastava, Dennis Sylvester, David Blaauw.
260 $aNew York :$bSpringer,$cc2005.
300 $aix, 279 p. :$bill. ;$c25 cm.
504 $aIncludes bibliographical references (p. [265]-276) and index.
650 0 $aIntegrated circuits$xVery large scale integration$xPower supply $xDesign and construction$xStatistical methods.
650 0 $aTiming circuits$xDesign and construction$xStatistical methods.
650 0 $aMathematical optimization.
700 1 $aSylvester, Dennis.
700 1 $aBlaauw, David.
938 $aBaker & Taylor$bBKTY$c129.00$d129.00$i0387257381$n0006476989$sactive
949 $aTK 7874.75 .S72 2005$i31786102045793
994 $a92$bCNU
999 $aTK 7874.75 .S72 2005$wLC$c1$i31786102045793$lCIRCSTACKS$mNULS$rY$sY $tBOOK$u1/3/2006