Record ID | marc_loc_updates/v36.i27.records.utf8:12674560:1609 |
Source | Library of Congress |
Download Link | /show-records/marc_loc_updates/v36.i27.records.utf8:12674560:1609?format=raw |
LEADER: 01609nam a22003014a 4500
001 2008274629
003 DLC
005 20080702104720.0
008 080627s2007 caua sb 101 0 eng
010 $a 2008274629
020 $a076953077X
020 $a9780769530772
040 $aDLC$cDLC
050 00 $aQA76.9.A73$bI568 2007
111 2 $aInternational Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems$d(2007 :$cMaui, Hawaii)
245 10 $aInnovative architecture for future generation high-performance processors and systems :$bIWIA 2007, 11-13 January 2007, Maui, Hawaii, USA /$cedited by Atsushi Kubota, Alexander V. Veidenbaum.
260 $aLos Alamitos, Calif. :$bCPS, IEEE Computer Society,$cc2007.
300 $a120 p. :$bill. ;$c29 cm.
500 $a"The chapters of this edited volume presents original research first publicly revealed at the 2007 International Workship on Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'5 [sic])"--Message from the editors.
500 $a"IEEE Computer Society order number P3077"--T.p. verso.
504 $aIncludes bibliographical references and index.
650 0 $aComputer architecture$vCongresses.
650 0 $aHigh performance computing$vCongresses.
650 0 $aHigh performance processors$vCongresses.
700 1 $aKubota, Atsushi.
700 1 $aVeidenbaum, Alex.
710 2 $aUniversity of California, Irvine.$bCenter for Embedded Computer Systems.
740 0 $aInnovative Architecture for Future Generation High-Performance Processors and Systems, 2003.