| Record ID | marc_loc_2016/BooksAll.2016.part31.utf8:207471541:1191 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_2016/BooksAll.2016.part31.utf8:207471541:1191?format=raw |
LEADER: 01191cam a22003014a 4500
001 2004218911
003 DLC
005 20070831032702.0
008 040303s2002 ja a b f001 0 jpn
010 $a 2004218911
035 $a(CStRLIN)DCLP04-B3683
040 $aDLC-R$cDLC-R$dDLC-R$dDLC
042 $apcc
050 00 $aTK7874$b.I5964 2002
066 $c$1
245 00 $6880-01$aIT jidai no jissō gijutsu :$bshisutemu in pakkēji gijutsu.
260 $6880-02$aTōkyō :$bTokkyochō,$cHeisei 14 [2002]
300 $a271 p. :$bill. (some col.) ;$c30 cm.
440 0 $6880-03$aHeisei 13-nendo tokkyo shutsugan gijutsu dōkō chōsa bunseki hōkokusho
500 $aCover title.
504 $aIncludes bibliographical references and indexes.
650 0 $aIntegrated circuits$xPatents.
650 0 $aIntegrated circuits$xDesign and construction.
710 1 $6880-04$aJapan.$bTokkyochō.
880 00 $6245-01/$1$aIT 時代の実装技術 :$bシステム・イン・パッケージ技術.
880 $6260-02/$1$a東京 :$b特許庁,$c平成 14 [2002]
880 0 $6440-03/$1$a平成 13年度特許出願技術動向調查分析報告書
880 1 $6710-04/$1$aJapan.$b特許庁.