MARC Record from Library of Congress

LEADER: 03295cam a2200409 a 4500
001 97202128
003 DLC
005 19981202112743.7
008 970910s1997 caua b 101 0 eng d
010 $a 97202128
020 $a0818680997 (paper)
020 $a0818681004 (case)
020 $a0818681012 (microfiche)
035 $a(OCoLC)37597894
040 $aMdFmN$cMdFmN$dPPiC$dDLC
042 $alccopycat
050 04 $aTK7895.M4$bI334 1997
082 00 $a621.39/732$221
111 2 $aIEEE International Workshop on Memory Technology, Design, and Testing$d(1997 :$cSan Jose, Calif.)
245 10 $aProceedings :$bInternational Workshop on Memory Technology, Design, and Testing /$cedited by F. Lombardi, R. Rajsuman, and T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Council.
246 14 $aRecords of the IEEE International Workshop on Memory Technology, Design and Testing
246 30 $aMemory Technology, Design and Testing
246 30 $aMTDT'97
260 $aLos Alamitos, Calif. :$bIEEE Computer Society Press,$cc1997.
300 $aix, 103 p. :$bill. ;$c28 cm.
500 $a"August 11-12, 1997, San Jose, California"--Cover.
500 $a"IEEE Order Plan Catalog Number 95TB100159"--T.p. verso.
500 $a"IEEE Computer Society Order Number PR08099"--T.p. verso.
504 $aIncludes bibliographical references and index.
505 0 $a Matching memory to the power of personal computers / R. Foss -- A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.] -- High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.] -- An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev -- SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen -- False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley -- A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker -- Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant -- A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao -- A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.] -- Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang -- An open notation for memory tests / A. Offerman, A. van de Goor -- Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.] -- Memory array testing through a scannable configuration / S. Yano, N. Ishiura -- A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.].
650 0 $aSemiconductor storage devices$xTesting$xCongresses.
650 0 $aRandom access memory$xCongresses.
700 1 $aLombardi, Fabrizio,$d1955-
700 1 $aRajsuman, Rochit.
700 1 $aWik, T.$q(Thomas)
710 2 $aIEEE Computer Society.$bTest Technology Technical Committee.
710 2 $aIEEE Computer Society.$bTechnical Committee on VLSI.