MARC Record from marc_columbia

LEADER: 12898cam a2200421 a 4500
001 7142060
005 20221130211227.0
008 030416s2003 njua b 001 0 eng d
010 $a 2003535257
015 $aGBA3-Z3528
019 $a51482308
020 $a0471447277
020 $a9780471447276
029 1 $aUKM$bbA3Z3528
029 1 $aAU@$b000024608593
035 $a(OCoLC)ocm51933611
035 $a(NNC)7142060
035 $a7142060
040 $aIMJ$cIMJ$dDLC$dUKM$dBAKER$dBTCTA$dYDXCP$dOrLoB-B
042 $alccopycat
050 00 $aTK7872.P38$bP48 2003
082 00 $a621.3815/364$221
245 00 $aPhase-locking in high-performance systems :$bfrom devices to architectures /$cedited by Behzad Razavi.
260 $aPiscataway, New Jersey :$bIEEE ;$aHoboken, New Jersey :$bWiley-Interscience,$c2003.
300 $axiii, 716 pages :$billustrations ;$c29 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
505 00 $gPt. I.$tOriginal Contributions -- $tDevices and Circuits for Phase-Locked Systems /$rB. Razavi -- $tDelay-Locked Loops - An Overview /$rC.-K. Ken Yang -- $tDelta-Sigma Fractional-N Phase-Locked Loops /$rI. Galton -- $tDesign Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems /$rR. C. Walker -- $tPredicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers /$rK. S. Kundert -- $gPt. II.$tDevices -- $tPhysics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors /$rS. Jenei, B. K. J. C. Nauwelaers and S. Decoutere -- $tThe Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's /$rJ. R. Long and M. A. Copeland -- $tAnalysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's /$rA. M. Niknejad and R. G. Meyer -- $tStacked Inductors and Transformers in CMOS Technology /$rA. Zolfaghari, A. Chan and B. Razavi -- $tEstimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies /$rK. O -- $tA Q-Factor Enhancement Technique for MMIC Inductors /$rM. Danesh, J. R. Long, R. A. Hadaway and D. L. Harame -- $tOn-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's /$rC. Patrick Yue and S. S. Wong -- $tThe Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors /$rS.-M. Yim, T. Chen and K. O -- $tTemperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a Silicon-Germanium/BiCMOS Technology /$rR. Groves, D. L. Harame and D. Jadus -- $tSubstrate Noise Coupling Through Planar Spiral Inductor /$rA. L. Pun, T. Yeung, J. Lau, F. J. R. Clement and D. K. Su -- $tDesign of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process /$rA.-S. Porret, T. Melly, C. C. Enz and E. A. Vittoz -- $tOn the Use of MOS Varactors in RF VCO's /$rP. Andreani and S. Mattisson -- $gPt. III.$tPhase Noise and Jitter -- $tLow-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks /$rJ.Craninckx and M. Steyaert -- $tA Study of Phase Noise in CMOS Oscillators /$rB. Razavi -- $tA General Theory of Phase Noise in Electrical Oscillators /$rA. Hajimiri and T. H. Lee -- $tPhysical Processes of Phase Noise in Differential LC Oscillators /$rJ. J. Rael and A. A. Abidi -- $tPhase Noise in LC Oscillators /$rK. A. Kouznetsov and R. G. Meyer -- $tThe Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs /$rJ. W. M. Rogers, J. A. Macedo and C. Plett -- $tJitter in Ring Oscillators /$rJ. A. McNeill -- $tJitter and Phase Noise in Ring Oscillators /$rA. Hojimiri, S. Limotyrakis and T. H. Lee -- $tA Study of Oscillator Jitter Due to Supply and Substrate Noise /$rF. Herzel and B. Razavi -- $tMeasurements and Analysis of PLL Jitter Caused by Digital Switching Noise /$rP. Larsson -- $tOn-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops /$rB. R. Veillette and G. W. Roberts -- $gPt. IV.$tBuilding Blocks -- $tA Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications /$rM. A. Margarit, J. L. Tham, R. G. Meyer and M. J. Deen -- $tA Fully Integrated VCO at 2 GHz /$rM. Zannoth, B. Kolb, J. Fenk and R. Weigel -- $tTail Current Noise Suppression in RF CMOS VCOs /$rP. Andreani and H. Sjoland -- $tLow-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS /$rM. Tiebout -- $tAnalysis and Design of an Optimally Coupled 5-GHz Quadrature LC Oscillator /$rJ. van der Tang, P. van de Ven, D. Kasperkovitz and A. van Roermund -- $tA 1.57-GHz Fully Integrated Very Low-Phase-Noise Quadrature VCO /$rP. Vancorenland and M. S. J. Steyaert -- $tA Low-Phase-Noise 5GHz Quadrature CMOS VCO Using Common-Mode Inductive Coupling /$rS. L. J. Gierkink, S. Levantino, R. C. Frye and V. Boccuzzi -- $tAn Integrated 10/5GHz Injection-Locked Quadrature LC VCO in a 0.18[mu]m Digital CMOS Process /$rA. Ravi, K. Soumyanath, L. R. Carley and R. Bishop -- $tRotary Traveling-Wave Oscillator Arrays: A New Clock Technology /$rJ. Wood and S. Lipa -- $t35-GHz Static and 48-GHz Dynamic Frequency Divider IC's Using 0.2-[mu]m AlGaAs/GaAs-HEMT's /$rZ. Lao, W. Bronner, A. Thiede, M. Schlechtweg, A. Hulsmann, M. Rieger-Motzer, G. Kaufel, B. Raynor and M. Sedler -- $tSuperharmonic Injection-Locked Frequency Dividers /$rH. R. Rategh and T. H. Lee -- $tA Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-[mu]m CMOS Technology /$rC. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli and Z. Wang -- $tA 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-[mu]m CMOS /$rJ. Craninckx and M. S. J. Steyaert -- $tA 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops /$rB. Chang, J. Park and W. Kirn -- $tHigh-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler /$rP. Larsson -- $tA 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC) /$rJ. N. Soares, Jr. and W. A. M. Van Noije -- $tA Simple Precharged CMOS Phase Frequency Detector /$rH. O. Johansson -- $gPt. V.$tClock Generation by PLLs and DLLs -- $tA 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation /$rV. von Kaenel, D. Aebischer, C. Piguet and E. Dijkstra -- $tA Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3 V/5 V Operation /$rH. C. Yang, L. K. Lee and R. S. Co -- $tLow-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques /$rJ. G. Maneatis -- $tA Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz /$rD. W. Boerstler -- $tA 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL /$rS. Kim, K. Lee, Y. Moon, D.-K. Jeong, Y. Choi and H. K. Lim -- $tActive GHz Clock Network Using Distributed PLLs /$rV. Gutnik and A. P. Chandrasakan -- $tA Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control /$rJ. Lee and B. Kim -- $tA Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-[mu]m CMOS PLL Based on a Sample-Reset Loop Filter /$rA. Maxim, B. Scott, E. M. Schneider, M. L. Hagge, S. Chacko and D. Stiurca -- $tA Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines /$rY.-J. Jung, S.-W. Lee, D. Shim, W. Kim and C. Kim -- $tAn All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance /$rY. Moon, J. Choi, K. Lee, D.-K. Jeong and M.-K. Kim -- $tA Semidigital Dual Delay-Locked Loop /$rS. Sidiropoulos and M. A. Horowitz -- $tA Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle /$rH.-H. Chang, J.-W. Lin, C.-Y. Yang and S.-I. Liu -- $tA Portable Digital DLL for High-Speed CMOS Interface Circuits /$rB. W. Garlepp, K. S. Donnelly, J. Kim, P. S. Chau, J. L. Zerbe, C. Huang, C. V. Tran, C. L. Portmann, D. Stark, Y.-F. Chan, T. H. Lee and M. A. Horowitz -- $tCMOS DLL-Base 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator /$rC. J. Foley and M. P. Flynn -- $tA 1.5V 86 mW/ch 8-Channel 622-3125-Mb/s/ch CMOS SerDes Macrocell with Selectable Mux/Demux Ratio /$rF. Yang, J. O'Neill, P. Larsson, D. Inglis and J. Othmer -- $tA Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM /$rF. Lin, J. Miller, A. Schoenfeld, M. Ma and R. J. Baker -- $tA Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM /$rS. J. Kim, S. H. Hong, J.-K. Wee, J. H. Cho, P. S. Lee, J. H. Ahn and J. Y. Chung -- $gPt. VI.$tRF Synthesis -- $tAn Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time /$rC. S. Vaucher -- $tA 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers /$rW. S. T. Yan and H. C. Luong -- $tA CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver /$rH. R. Rategh, H. Samavati and T. H. Lee -- $tA 2.6-GHz/5.2-GHz Frequency Synthesizer in 0.4-[mu]m CMOS Technology /$rC. Lam and B. Razavi -- $tFast Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector /$rC.-Y. Yang and S.-I. Liu --
500 $a"A selected reprint volume."
504 $aIncludes bibliographical references and index.
505 80 $tLow-Power Dividerless Frequency Synthesis Using Aperture Phase Detection /$rA. R. Shahani, D. K. Shaeffer, S. S. Mohan, H. Samavati, H. R. Rategh, M. del M. Hershenson, M. Xu, C. P. Yue, D. J. Eddleman, M. A. Horowitz and T. H. Lee -- $tA Stabilization Technique for Phase-Locked Frequency Synthesizers /$rT.-C. Lee and B. Razavi -- $tA Modeling Approach for [Sigma]-[Delta] Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis /$rM. H. Perrott, M. D. Trott and C. G. Sodini -- $tA Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems /$rY. Koo, H. Huh, Y. Cho, J. Lee, J. Park, K. Lee, D.-K. Jeong and W. Kim -- $tA 1.1-GHz CMOS Fraction-N Frequency Synthesizer With a 3-b Third-Order [Sigma]-[Delta] Modulator /$rW. Rhee, B.-S. Song and A. Ali -- $tA 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching /$rC.-H. Park, O. Kim and B. Kim -- $tA 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation /$rM. H. Perrott, T. L. Tewksbury III and C. G. Sodini -- $tA CMOS Monolothic [Sigma][Delta]-Controlled Fractional-N Frequency Synthesizer for DSC-1800 /$rB. De Mauer and M. S. J. Steyaert -- $gPt. VII.$tClock and Data Recovery -- $tA 2.5-Gb/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN's and WAN's /$rK. Kishine, N. Ishihara, K. Takiguchi and H. Ichino -- $tClock/Data Recovery PLL Using Half-Frequency Clock /$rM. Rau, T. Oberst, R. Lares, A. Rothermel, R. Schweer and N. Menoux -- $tA 0.5-[mu]m CMOS 4.0-Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling /$rC.-K. K. Yang, R. Farjad-Rad and M. A. Horowitz -- $tA 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability /$rP. Larsson -- $tSiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb/s SONET Application /$rY. M. Greshishchev and P. Schvan -- $tA Fully Integrated SiGe Receiver IC for 10-Gb/s Data Rate /$rY. M. Greshishchev, P. Schvan, J. L. Showell, M.-L. Xu, J. J. Ojha and J. E. Rogers -- $tA 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector /$rJ. Savoj and B. Razavi -- $tA 10-Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection /$rJ. Savoj and B. Razavi -- $tA 10-Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18[mu]m CMOS /$rJ. E. Rogers and J. R. Long -- $tA 40-Gb/s Integrated Clock and Data Recovery Circuit in a 50-GHz f[subscript T] Silicon Bipolar Technology /$rM. Wurzer, J. Bock, H. Knapp, W. Zirwas, F. Schumann and A. Felder -- $tA Fully Integrated 40-Gb/s Clock and Data Recovery IC With 1:4 DEMUX in SiGe Technology /$rM. Reinhold, C. Dorschky, E. Rose, R. Pullela, P. Mayer, F. Kunz, Y. Baeyens, T. Link and J.-P. Mattia -- $tClock and Data Recovery IC for 40-Gb/s Fiber-Optic Receiver /$rG. Georgiou, Y. Baeyens, Y.-K. Chen, A. H. Gnauck, C. Gropper, P. Paschke, R. Pullela, M. Reinhold, C. Dorschky, J.-P. Mattia, T. Winkler von Mohrenfels and C. Schulien.
650 0 $aPhase-locked loops.$0http://id.loc.gov/authorities/subjects/sh85100640
650 0 $aHigh performance computing.$0http://id.loc.gov/authorities/subjects/sh95008935
700 1 $aRazavi, Behzad.$0http://id.loc.gov/authorities/names/n94062108
856 42 $3Contributor biographical information$uhttp://www.loc.gov/catdir/bios/wiley046/2003535257.html
856 42 $3Publisher description$uhttp://www.loc.gov/catdir/description/wiley039/2003535257.html
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/enhancements/fy0616/2003535257-t.html
852 00 $boff,eng$hTK7872.P38$iP48 2003