MARC Record from marc_columbia

LEADER: 07043cam a2200337Ia 4500
001 6020360
005 20221121224554.0
008 061219t20062006paua b 101 0 eng d
020 $a9781558998698
020 $a1558998691
035 $a(OCoLC)ocm77118277
035 $a(NNC)6020360
035 $a6020360
040 $aLHL$cLHL$dOrLoB-B
090 $aTK7871.9$b.T72 2006
245 00 $aTransistor scaling--methods, materials and modeling :$bsymposium held April 18-19, 2006, San Francisco, California, U.S.A. /$ceditors: Scott Thompson [and others].
260 $aWarrendale, Pa. :$bMaterials Research Society,$c[2006], ©2006.
300 $aix, 205 pages :$billustrations ;$c24 cm.
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
490 1 $aMaterials Research Society symposium proceedings ;$vv. 913
500 $a"Symposium D, 'Transistor Scaling--Methods, Materials and Modeling,,' [was] held on April 18-19 at the 2006 MRS Spring Meeting in San Francisco, California ..."--Pref.
504 $aIncludes bibliographical references and indexes.
505 00 $tAmorphization/templated recrystallization (ATR) method for hybrid orientation substrates /$rK. L. Saenger, J. P. de Souza, K. E. Fogel, J. A. Ott, A. Reznicek, C. Y. Sung, H. Yin and D. K. Sadana -- $tSystematic characterization of pseudomorphic (110) intrinsic SiGe epitaxial films for hybrid orientation technology with embedded SiGe source/drain /$rQiqing (Christine) Ouyang, Anita Madan, Nancy Klymko, Jinghong Li, Richard Murphy, Horatio Wildman, Robert Davis, Conal Murray, Judson Holt, Siddhartha Panda, Meikei Jeong and Chun-Yung Sung -- $tSchottky source/drain transistor on thin SiGe on insulator integrated with HfO[subscript 2]/TaN gate stack /$rFei Gao, S. J. Lee, Rui Li, S. Balakumar, Chih-Hang Tung, Dong-Zhi Chi and Dim-Lee Kwong -- $tSchottky-barrier height tuning using dopant segregation in Schottky-barrier MOSFETs on fully-depleted SOI /$rJoachim Knoch, Min Zhang, Qing-Tai Zhao and Siegfried Mantl -- $tVisualization of Ge condensation in SOI /$rKristel Fobelets, Benjamin Vincent, Munir Ahmad, Astolfi Christofi and David McPhail -- $tStructure and process parameter optimization for sub-10 nm gate length fully depleted N-type SOI MOSFETs by TCAD modeling and simulation /$rYawei Jin, Lei Ma, Chang Zeng, Krishnanshu Dandu and Doug William Barlage -- $tA novel high-stress pre-metal dielectric film to improve device performance for sub-65 nm CMOS manufacturing /$rYoung Way Teh, John Sudijono, Alok Jain, Shankar Venkataraman, Sunder Thirupapuliyur and Harry Whitesell -- $tMobility enhancement by strained nitride liners for 65 nm CMOS logic design features /$rClaude Ortolland, Pierre Morin, Franck Arnaud, Stephane Orain, Chandra Reddy, Catherine Chaton and Peter Stolk -- $tProcess-induced strained P-MOSFET featuring nickel-platinum silicided source/drain /$rRinus Tek Po Lee, Tsung-Yang Liow, Kian-Ming Tan, Kah-Wee Ang, King-Jien Chui, Qiang-Lo Guo, Ganesh Samudra, Dong-Zhi Chi and Yee-Chia Yeo -- $tThermal stability of thin virtual substrates for high performance devices /$rSarah H. Olsen, Steve J. Bull, Peter Dobrosz, Enrique Escobedo-Cousin, Rimoon Agaiby, Anthony G. O'Neill, Howard Coulson, Cor Claeys, Roger Loo, Romain Delhougne and Matty Caymax -- $tImpact of heavy boron doping and nickel germanosilicide contacts on biaxial compressive strain in pseudomorphic silicon-germanium alloys on silicon /$rSaurabh Chopra, Mehmet C. Ozturk, Veena Misra, Kris McGuire and Laurie McNeil -- $tEvidence of reduced self heating with partially depleted SOI MOSFET scaling /$rGeorges Guegan, Romain Gwoziecki, Oliver Gonnard, Gilles Gouget, Christine Raynaud, Mikael Casse and Simon Delenibus -- $tQuantum well nanopillar transistors /$rShu-Fen Hu and Chin-Lung Sung -- $tEffect of spacer scaling on PMOS transistors /$rWai Shing Lau, Chee Wee Eng, David Vigar, Lap Chan and Soh Yun Siah -- $tLow temperature silicon dioxide deposition and characterization /$rHood Chatham, Martin Mogaard, Yoshi Okuyama and Helmuth Treichel -- $tBCl[subscript 3]/N[subscript 2] plasma for advanced non-Si gate patterning /$rDenis Shamiryan, Vasile Paraschiv, Salvador Eslava-Fernandez, Marc Demand, Mihail Baklanov and Werner Boullart -- $tLayer transfer of hydrogen-implanted silicon wafers by thermal-microwave co-activation /$rY. Y. Yang, C. H. Huang, Y.-K. Hsu, S.-J. Jeng, C.-C. Tai, S. Lee, H.-W. Chen, Q. Gan, C.-S. Chu, J.-H. Ting, C. S. Lai and T.-H. Lee -- $tIntroduction of airgap deeptrench isolation in STI module for high speed SiGe : C BiCMOS technology /$rEddy Kunnen, Li Jen Choi, Stefaan Van Huylenbroeck, Andreas Piontec, Frank Vleugels, Tania Dupont, Katia Devriendt, Xiaoping Shi, Serge Vanhaelemeersch and Stefaan Decoutere -- $tLow temperature selective Si and Si-based alloy epitaxy for advanced transistor applications /$rYihwan Kim, Ali Zojaji, Zhiyuan Ye, Andrew Lam, Nicholas Dalida, Errol Sanchez and Satheesh Kuppurao -- $tNano-scale MOSFET devices fabricated using a novel carbon-nanotube-based lithography /$rJaber Derakhshandeh, Yaser Abdi, Shams Mohajerzadeh, Mohammad Beikahmadi, Ashkan Behnam, Ezatollah Arzi, Michael D. Robertson and C. J. Bennett -- $tElectron thermal transport properties of a quantum dot /$rXanthippi Zianni -- $tUsing quantitative TEM analysis of implant damage to study surface recombination velocity in silicon /$rJennifer Lee Gasky, Sophya Morghem and Kevin Jones -- $tDiffraction from periodic arrays of oxide-filled trenches in silicon : investigation of local strains /$rMichel Eberlein, Stephanie Escoubas, Marc Gailhanou, Olivier Thomas, Pascal Rohr and Romain Coppard -- $tStress and strain measurements in semiconductor device channel areas by convergent beam electron diffraction /$rJinghong Li, Anthony Domenicucci, Dureseti Chidambarrao, Brian Greene, Nivo Rovdedo, Judson Holt, Drerren Dunn and Hung Ng -- $tA physically based quantum correction model for DG MOSFETs /$rMarkus Karner, Martin Wagner, Tibor Grasser and Hans Kosina -- $tTCAD modeling of strain-engineered MOSFETs /$rLee Smith -- $tPredictive model for B diffusion in strained SiGe based on atomistic calculations /$rChihak Ahn, Jakyoung Song and Scott T. Dunham -- $t3D modeling of the novel nanoscale screen-grid FET /$rPei W. Ding, Kristel Fobelets and Jesus E. Velazquez-Perez -- $tTCAD modeling and simulation of sub-100 nm gate length silicon and GaN based SOI MOSFETs /$rLei Ma, Yawei Jin, Chang Zeng, Krishnanshu Dandu, Mark Johnson and Doug William Barlage.
650 0 $aTransistors$vCongresses.
650 0 $aTransistor circuits$vCongresses.
700 1 $aThompson, Scott.$0http://id.loc.gov/authorities/names/n96063735
710 2 $aMaterials Research Society.$bFall Meeting$d(2006 :$cSan Francisco, Calif.)
711 2 $aSymposium on Transistor Scaling--Methods, Materials and Modeling$d(2006 :$cSan Francisco, Calif.)
830 0 $aMaterials Research Society symposia proceedings ;$vv. 913.$0http://id.loc.gov/authorities/names/n42037756
852 00 $boff,eng$hTK7871.9$i.T72 2006g