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LEADER: 03758mam a2200421 a 4500
001 2009465
005 20220609051102.0
008 970910t19971997caua b 101 0 eng d
020 $a0818680997 (paper)
020 $a0818681004 (case)
020 $a0818681012 (microfiche)
035 $a(OCoLC)ocm37597894
035 $9AMN7441CU
035 $a2009465
040 $aNSA$cNSA$dOrLoB-B
111 2 $aIEEE International Workshop on Memory Technology, Design, and Testing$d(1997 :$cSan Jose, Calif.)
245 10 $aProceedings :$bInternational Workshop on Memory Technology, Design, and Testing /$cedited by F. Lombardi, R. Rajsuman, and T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Council.
246 14 $aRecords of the IEEE International Workshop on Memory Technology, Design and Testing
246 30 $aMemory Technology, Design and Testing
246 30 $aMTDT'97
260 $aLos Alamitos, Calif. :$bIEEE Computer Society Press,$c[1997], ©1997.
300 $aix, 103 pages :$billustrations ;$c28 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
500 $a"August 11-12, 1997, San Jose, California"--Cover.
500 $a"IEEE Order Plan Catalog Number 95TB100159"--T.p. verso.
500 $a"IEEE Computer Society Order Number PR08099"--T.p. verso.
504 $aIncludes bibliographical references and index.
505 00 $tMatching Memory to the Power of Personal Computers /$rR. Foss --$tA Low-Cost, High Performance Three-Dimensional Memory Module Technology /$rA. Glaser, M. Nakkar and P. Franzon [et al.] --$tHigh Speed Circuit Techniques in a 150MHz 64M SDRAM /$rV. Lines, M. Abou-Seido and C. Mar [et al.] --$tAn Analysis of (Linked) Addressed Decoder Faults /$rA. van de Goor and G. Gaydadjiev --$tSRAM Yield Estimation in the Early Stage of the Design Cycle /$rV. Kim and T. Chen --$tFalse Write Through and Un-Restored Write Electrical Level Fault Models for SRAMs /$rR. Adams and E. Cooley --$tA Defect-Tolerant DRAM Employing a Hierarchical Redundancy Scheme, Built-In Self-Test and Self-Reconfiguration /$rD. Niggemeyer, J. Otterstedt and M. Redeker --$tFormal Verification of Memory Arrays using Symbolic Trajectory Evaluation /$rM. Pandey and R. Bryant --$tA Product Development Flow with Metrics for Memory Designs /$rS. Hegde, I. Pal and K. Rao --
505 80 $tA Low-Power High Storage Capacity Structure for GaAs MESFET ROM /$rR. Kanan, B. Hochet and M. Declercq [et al.] --$tUse of Selective Precharge for Low-Power on the Match Lines of Content-Addressable Memories /$rC. Zukowski and S. Wang --$tAn Open Notation for Memory Tests /$rA. Offerman and A. van de Goor --$tTesting Memory Modules in SRAM-Based Configurable FPGAs /$rW. Huang, F. Meyer and N. Park [et al.] --$tMemory Array Testing through a Scannable Configuration /$rS. Yano and N. Ishiura --$tA High-Speed Parallel Sensing Scheme for Multi-Level Non-Volatile Memories /$rC. Calligaro, A. Manstretta and G. Torelli [et al.].
650 0 $aSemiconductor storage devices$xTesting$vCongresses.
650 0 $aRandom access memory$vCongresses.
700 1 $aLombardi, Fabrizio,$d1955-$0http://id.loc.gov/authorities/names/n88055522
700 1 $aRajsuman, Rochit.$0http://id.loc.gov/authorities/names/n89658334
700 1 $aWik, T.$q(Thomas)$0http://id.loc.gov/authorities/names/n97103014
710 2 $aIEEE Computer Society.$bTest Technology Technical Committee.$0http://id.loc.gov/authorities/names/n88164000
710 2 $aIEEE Computer Society.$bTechnical Committee on VLSI.$0http://id.loc.gov/authorities/names/n91120720
852 00 $boff,eng$hTK7895.M4$iI335 1997g