| Record ID | marc_columbia/Columbia-extract-20221130-004.mrc:574886953:1593 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-004.mrc:574886953:1593?format=raw |
LEADER: 01593fam a2200337 a 4500
001 1953572
005 20220609034518.0
008 960816s1997 caua b 001 0 eng
010 $a 96042114
020 $a0124343309 (alk. paper)
035 $a(OCoLC)35317862
035 $a(OCoLC)ocm35317862
035 $9AMF3603CU
035 $a(NNC)1953572
035 $a1953572
040 $aDLC$cDLC$dDLC$dNNC$dOrLoB-B
050 00 $aTK7874.75$b.L35 1997
082 00 $a621.39/5/0287$220
100 1 $aLala, Parag K.,$d1948-$0http://id.loc.gov/authorities/names/n84006930
245 10 $aDigital circuit testing and testability /$cParag K. Lala.
260 $aSan Diego, Calif. :$bAcademic Press,$c1997.
263 $a9701
300 $axii, 199 pages :$billustrations ;$c24 cm
336 $atext$btxt$2rdacontent
337 $aunmediated$bn$2rdamedia
504 $aIncludes bibliographical references and index.
505 00 $gCh. 1.$tFaults in Digital Circuits --$gCh. 2.$tTest Generation for Combinational Logic Circuits --$gCh. 3.$tTestable Combinational Logic Circuit Design --$gCh. 4.$tTest Generation for Sequential Circuits --$gCh. 5.$tDesign of Testable Sequential Circuits --$gCh. 6.$tBuilt-In Self Test --$gCh. 7.$tTestable Memory Design --$gApp.$tMarkov Models.
650 0 $aIntegrated circuits$xVery large scale integration$xTesting.$0http://id.loc.gov/authorities/subjects/sh2009127319
650 0 $aDigital integrated circuits$xTesting.
650 0 $aIntegrated circuits$xFault tolerance.$0http://id.loc.gov/authorities/subjects/sh96008890
852 00 $boff,eng$hTK7874.75$i.L35 1997