| Record ID | marc_columbia/Columbia-extract-20221130-001.mrc:413808123:1728 |
| Source | marc_columbia |
| Download Link | /show-records/marc_columbia/Columbia-extract-20221130-001.mrc:413808123:1728?format=raw |
LEADER: 01728cam a2200409 a 4500
001 330592
005 20220519001835.0
008 850402t19841984maua b 001 0 eng
010 $a 84015490
020 $a0898381649
035 $a(OCoLC)10998529
035 $a(OCoLC)ocm10998529
035 $a(CStRLIN)NYCG85-B34088
035 $9ABL6512CU
035 $a(NNC)330592
035 $a330592
040 $dCStRLIN
050 00 $aTK7868.L6$bL626 1984
082 0 $a621.381/73$219
090 $aTK7868.L6$bL626 1984
245 00 $aLogic minimization algorithms for VLSI synthesis /$cby Robert K. Brayton [and others].
260 $aBoston :$bKluwer Academic Publishers,$c[1984], ©1984.
300 $aix, 193 pages :$billustrations ;$c25 cm.
336 $atext$2rdacontent
337 $aunmediated$2rdamedia
338 $avolume$2rdacarrier
490 1 $aThe Kluwer international series in engineering and computer science
504 $aBibliography: p. [174]-190.
500 $aIncludes index.
650 0 $aLogic design.$0http://id.loc.gov/authorities/subjects/sh85078117
650 0 $aIntegrated circuits$xVery large scale integration.$0http://id.loc.gov/authorities/subjects/sh85067125
650 0 $aIntegrated circuits$xDesign and construction$xData processing.$0http://id.loc.gov/authorities/subjects/sh85067119
650 0 $aAlgorithms.$0http://id.loc.gov/authorities/subjects/sh85003487
700 1 $aBrayton, Robert King.$0http://id.loc.gov/authorities/names/n79031222
740 0 $aLogic minimization algorithms for V.L.S.I. synthesis.
830 0 $aKluwer international series in engineering and computer science.$0http://id.loc.gov/authorities/names/n84749953
852 00 $boff,eng$hTK7868.L6$iL626 1984