MARC record from Internet Archive

LEADER: 02033cam 2200337Ma 4500
001 9922120110001661
005 20150423142418.0
008 040416s2006 nyua 001 0 eng d
020 $a0387333991
035 $a(CSdNU)u283756-01national_inst
035 $a(OCoLC)71414068
035 $a(OCoLC)71414068
040 $aZCU$cZCU$dOrLoB-B
049 $aCNUM
050 4 $aTK7885.7$b.S876 2006
100 1 $aSutherland, Stuart,$d1953-
245 10 $aSystemVerilog for design :$ba guide to using SystemVerilog for hardware design and modeling /$cby Stuart Sutherland, Simon Davidmann, Peter Flake ; foreword by Phil Moorby.
250 $a2nd ed.
260 $aNew York :$bSpringer,$c2006.
300 $axxx, 418 p. :$bill. ;$c25 cm.
500 $aIncludes index.
505 0 $aCh. 1. Introduction to SystemVerilog -- Ch. 2. SystemVerilog declaration spaces -- Ch. 3. SystemVerilog literal values and built-in data types -- Ch. 4. SystemVerilog user-defined and enumerated types -- Ch. 5. SystemVerilog arrays, structures and unions -- Ch. 6. SystemVerilog procedural blocks, tasks and functions -- Ch. 7. SystemVerilog procedural statements -- Ch. 8. Modeling finite state machines with SystemVerilog -- Ch. 9. SystemVerilog design hierarchy -- Ch. 10. SystemVerilog interfaces -- Ch. 11. A complete design modeled with SystemVerilog -- Ch. 12. Behavioral and transaction level modeling -- App. A. The SystemVerilog formal definition (BNF) -- App. B. Verilog and SystemVerilog reserved keywords -- App. C. A history of SUPERLOG, the beginning of SystemVerilog.
650 0 $aVerilog (Computer hardware description language)
650 0 $aElectronic digital computers$xDesign and construction.
650 0 $aComputer simulation.
700 1 $aDavidmann, Simon.
700 1 $aFlake, Peter.
947 $fSOET-TEC$hCIRCSTACKS$p$107.50$q1
949 $aTK 7885.7 .S876 2006$i31786102303705
994 $a92$bCNU
999 $aTK 7885.7 .S876 2006$wLC$c1$i31786102303705$d10/1/2012$e8/20/2012 $lCIRCSTACKS$mNULS$rY$sY$tBOOK$u10/5/2006