| Record ID | ia:systemsynthesisw0000unse |
| Source | Internet Archive |
| Download MARC XML | https://archive.org/download/systemsynthesisw0000unse/systemsynthesisw0000unse_marc.xml |
| Download MARC binary | https://www.archive.org/download/systemsynthesisw0000unse/systemsynthesisw0000unse_meta.mrc |
LEADER: 01002cam a2200265 a 4500
001 97045518
003 DLC
005 20080311084954.0
008 971014s1998 maua b 001 0 eng
010 $a 97045518
020 $a0792380827 (hb : alk. paper)
040 $aDLC$cDLC$dDLC
050 00 $aQA76.9.S88$bE44 1998
082 00 $a621.39/2$221
245 00 $aSystem synthesis with VHDL /$cedited by Petru Eles, Krzysztof Kuchcinski, and Zebo Peng.
260 $aBoston :$bKluwer Academic Publishers,$cc1998.
300 $axiii, 370 p. :$bill. ;$c25 cm.
504 $aIncludes bibliographical references (p. [351]-363) and index.
650 0 $aSystem design.
650 0 $aVHDL (Computer hardware description language)
700 1 $aEles, Petru
700 1 $aKuchcinski, Krzysztof.
700 1 $aPeng, Zebo.
856 42 $3Publisher description$uhttp://www.loc.gov/catdir/enhancements/fy0820/97045518-d.html
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/enhancements/fy0820/97045518-t.html