| Record ID | ia:processorarchite0000silc |
| Source | Internet Archive |
| Download MARC XML | https://archive.org/download/processorarchite0000silc/processorarchite0000silc_marc.xml |
| Download MARC binary | https://www.archive.org/download/processorarchite0000silc/processorarchite0000silc_meta.mrc |
LEADER: 01018cam a22002774a 4500
001 99015706
003 DLC
005 20080307110759.0
008 990428s1999 gw a b 001 0 eng
010 $a 99015706
020 $a3540647988 (alk. paper)
040 $aDLC$cDLC$dDLC
042 $apcc
050 00 $aQA76.9.A73$bS456 1999
082 00 $a004.2/2$221
100 1 $aŠilc, Jurij,$d1956-
245 10 $aProcessor architecture :$bfrom dataflow to superscalar and beyond /$cJurij Šilc, Borut Robič, Theo Ungerer.
260 $aBerlin ;$aNew York :$bSpringer,$cc1999.
300 $axxii, 389 p. :$bill. ;$c24 cm.
504 $aIncludes bibliographical references and index.
650 0 $aComputer architecture.
650 0 $aMicroprocessors.
700 1 $aRobič, Borut,$d1960-
700 1 $aUngerer, Theo,$d1954-
856 42 $3Publisher description$uhttp://www.loc.gov/catdir/enhancements/fy0815/99015706-d.html
856 41 $3Table of contents only$uhttp://www.loc.gov/catdir/enhancements/fy0815/99015706-t.html