MARC record from Internet Archive

LEADER: 02616nam 2200385 a 4500
001 ocn640928158
005 20100714105348.2
008 990119s1992 caua b f000|0 eng d
035 $a
035 $a
040 $aCMontNP$cCMontNP
086 0 $aD 208.14/2:NPS-EC-92-004
100 1 $aDueck, Gerard W.
245 10 $aMultiple-valued programmable logic array minimization by simulated annealing /$cGerard W. Dueck, Robert C. Earle, Parthasarathy Tirumalai, Jon T. Butler.
260 $aMonterey, Calif. :$bNaval Postgraduate School ;$aSpringfield, Va. :$bAvailable from National Technical Information Service,$c[1992]
300 $a27 p. :$bill. ;$c28 cm.
500 $aTitle from cover.
500 $a"NPS-EC-92-004."
500 $a"February 10, 1992."
500 $aAD A248 620.
504 $aIncludes bibliographical references (p. 16-17)
520 $aWe propose a solution to the minimization problem of multiple-valued programmable logic arrays (PLA) that uses simulated annealing. The algorithm accepts a sum-of-products expression, divides and recombines the product terms, gradually progressing toward a minimal solution. The input expression can be user-specified or one produced by another heuristic. The process is termed simulated annealing because it has an analog in the statistical mechanical model of annealing in solids. That is, the slow cooling of certain solids results in a state of low energy, a crystalline state rather than an amorphous state that results from fast cooling. In a PLA, the crystalline state is analogous to a realization with a small number of product terms. Unlike recently studied minimization techniques (which are classified as direct cover methods), our technique manipulates product terms directly, breaking them up and joining them in different was while reducing the total number of product terms. Computer- aided design tool, multiple-valued logic, programmable logic array, heuristic minimization technique VLSI design tool.
650 4 $aANNEALING.
650 4 $aCOMPUTER AIDED DESIGN.
650 4 $aCOMPUTERIZED SIMULATION.
650 4 $aLOGIC CIRCUITS.
650 4 $aCOMPUTER PROGRAMS.
700 1 $aEarle, Robert C.
700 1 $aTirumalai, Parthasarathy.
700 1 $aButler, Jon T.
710 2 $aNaval Postgraduate School (U.S.).$bDept. of Electrical and Computer Engineering.
740 0 $aNPS-EC-92-004.
592 $aaq/aq cc:9116 01/19/99.
926 $aNPS-LIB$bDIGIPROJ$cD 208.14/2:NPS-EC-92-004$dBOOK$eNEVER$f1
926 $aNPS-LIB$bFEDDOCS$cD 208.14/2:NPS-EC-92-004$dBOOK$f2