MARC record from Internet Archive

LEADER: 08541aam a22005171a 4500
001 018373185
003 Uk
005 20170611023103.0
006 m || d |
007 cr |||||||||||
008 150130s2014 xx ob 001 0 eng d
015 $aGBB7A1379$2bnb
020 $a1322626308$q(ebk)
020 $a9781322626307$q(ebk)
020 $a1439895848
020 $a9781439895849
020 $a9781439895832
020 $a143989583X
037 $aTANDF_257440$bIngram Content Group
040 $aIDEBK$beng$cIDEBK$dCOO$dOCLCO$dOCLCF$dREB$dDEBSZ$dOCLCQ$dUk$epn
042 $aukblsr
050 4 $aQA76.9.A25$bM85 2015
082 04 $a005.8$223
100 1 $aMukhopadhyay, Debdeep.
245 10 $aHardware Security.
260 $a[Place of publication not identified] :$bCRC Press,$c2014.
300 $a1 online resource.
336 $atext$2rdacontent
337 $acomputer$2rdamedia
338 $aonline resource$2rdacarrier
504 $aIncludes bibliographical references and index.
505 0 $a<P><STRONG>Part I</STRONG></P><P><STRONG>Mathematical Background</STRONG></P><P>Introduction</P><P>Modular Arithmetic</P><P>Groups, Rings, and Fields</P><P>Greatest Common Divisors and Multiplicative Inverse</P><P>Subgroups, Subrings, and Extensions</P><P>Groups, Rings, and Field Isomorphisms</P><P>Polynomials and Fields</P><P>Construction of Galois Field</P><P>Extensions of Fields</P><P>Cyclic Groups of Group Elements</P><P>Efficient Galois Fields</P><P>Mapping between Binary and Composite Fields</P><P>Conclusions</P><P><STRONG>Overview of Modern Cryptography</STRONG></P><P>Introduction</P><P>Cryptography: Some Technical Details</P><P>Block Ciphers</P><P>Rijndael in Composite Field</P><P>Elliptic Curves</P><P>Scalar Multiplications: LSB First and MSB First Approaches</P><P>Montgomery’s Algorithm for Scalar Multiplication Inversions</P><P>Conclusions</P><P><STRONG>Modern Hardware Design Practices</STRONG></P><P>Introduction</P><P>Components of a Hardware Architecture: Mapping an Algorithm to Hardware</P><P>Case Study: Binary gcd Processor</P><P>Enhancing the Performance of a Hardware Design</P><P>Modelling of the Computational Elements of the gcd Processor</P><P>Experimental Results</P><P>Conclusions</P><P><STRONG>Hardware Design of the Advanced Encryption Standard (AES) </STRONG></P><P>Introduction</P><P>Algorithmic and Architectural Optimizations for AES Design </P><P>Circuit for the AES S-Box</P><P>Implementation of the Mix Column Transformation</P><P>An Example Reconfigurable Design for the Rijndael Cryptosystem</P><P>Experimental Results</P><P>Single Chip Encryptor/Decryptor</P><P>Conclusions</P><P><STRONG>Efficient Design of Finite Field Arithmetic on FPGAs </STRONG></P><P>Introduction</P><P>Finite Field Multiplier</P><P>Finite Field Multipliers for High Performance Applications </P><P>Karatsuba Multiplication</P><P>Karatsuba Multipliers for Elliptic Curves</P><P>Designing for the FPGA Architecture</P><P>Analyzing Karatsuba Multipliers on FPGA Platforms</P><P>Performance Evaluation</P><P>High Performance Finite Field Inversion Architecture for FPGAs</P><P>Itoh-Tsujii Inversion Algorithm</P><P>The Quad ITA Algorithm</P><P>Experimental Results</P><P>Generalization of the ITA for 2n Circuit</P><P>Hardware Architecture for 2n Circuit-Based ITA</P><P>Area and Delay Estimations for the 2n ITA</P><P>Obtaining the Optimal Performing ITA Architecture</P><P>Validation of Theoretical Estimations</P><P>Conclusions</P><P><STRONG>High Speed Implementation of Elliptic Curve Scalar Multiplication on FPGAs</STRONG></P><P>Introduction</P><P>The Elliptic Curve Cryptoprocessor</P><P>Point Arithmetic on the ECCP</P><P>The Finite State Machine (FSM)</P><P>Performance Evaluation</P><P>Further Acceleration Techniques of the ECC Processor</P><P>Pipelining Strategies for the Scalar Multiplier</P><P>Scheduling of the Montgomery Algorithm</P><P>Finding the Right Pipeline</P><P>Detailed Architecture of the ECM</P><P>Implementation Results</P><P>Conclusion</P><P><STRONG>Introduction to Side Channel Analysis</STRONG></P><P>Introduction</P><P>What Are Side Channels?</P><P>Types of Side Channel Attacks</P><P>Kocher’s Seminal Works</P><P>Power Attacks</P><P>Fault Attacks</P><P>Cache Attacks</P><P>Scan Chain-Based Attacks</P><P>Conclusions</P><P><STRONG>Differential Fault Analysis of Ciphers </STRONG></P><P>Introduction to Differential Fault Analysis</P><P>DFA and Associated Fault Models</P><P>Differential Fault Attacks on AES: Early Efforts</P><P>State of the Art DFAs on AES</P><P>Multiple Byte DFA of AES-128</P><P>Extension of the DFA to Other Variants of AES</P><P>DFA of AES Targeting the Key-Schedule</P><P>CED for AES</P><P>Conclusions</P><P><STRONG>Cache Attacks on Ciphers</STRONG></P><P>Memory Hierarchy and Cache Memory</P><P>Timing Attacks due to CPU Architecture</P><P>Trace-Driven Cache Attacks</P><P>Access-Driven Cache Attacks</P><P>Time-Driven Cache Attacks</P><P>Countermeasures for Timing Attacks</P><P>Conclusion</P><P><STRONG>Power Analysis of Cipher Implementations </STRONG></P><P>Power Attack Set up and Power Traces</P><P>Power Models</P><P>Differential Power Analysis using Difference of Mean</P><P>PKDPA: An Improvement of the DoM Technique</P><P>Correlation Power Attack</P><P>Metrics to Evaluate a Side Channel Analysis</P><P>CPA on Real Power Traces of AES-128</P><P>Popular Countermeasures against Power Analysis: Masking </P><P>Conclusions</P><P><STRONG>Testability of Cryptographic Hardware </STRONG></P><P>Introduction</P><P>Scan Chain-Based Attacks on Cryptographic Implementations </P><P>Scan Attack on Trivium</P><P>Testability of Cryptographic Designs</P><P>Conclusion</P><P><STRONG>Bibliography</STRONG></P><P><STRONG>Part II</STRONG></P><P><B>Hardware Intellectual Property Protection through Obfuscation</P></B><P>Introduction</P><P>Related Work</P><P>Functional Obfuscation through State Transition Graph Modification</P><P>Extension of STG Modification for RTL Designs</P><P>Obfuscation through Control and Data Flow Graph (CDFG) Modification</P><P>Measure of Obfuscation Level</P><P>Results</P><P>Discussions</P><P>Conclusions</P><B><P>Overview of Hardware Trojans</P></B><P>Introduction</P><P>Trojan Taxonomy and Examples</P><P>Multi-Level Attack</P><P>Effect of Hardware Trojan on Circuit Reliability</P><P>Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream</P><P>Conclusion</P><B><P>Logic Testing-Based Hardware Trojan Detection</P></B><P>Introduction</P><P>Statistical Approach for Trojan Detection</P><P>Results</P><P>Summary</P><B><P>Side-Channel Analysis Techniques for Hardware Trojans Detection</P></B><P>Introduction</P><P>Motivation for the Proposed Approaches</P><P>Multiple-Parameter Analysis-Based Trojan Detection</P><P>Results</P><P>Integration with Logic-Testing Approach</P><B><P>Design Techniques for Hardware Trojan Threat Mitigation</P></B><P>Introduction</P><P>Obfuscation-Based Trojan Detection/Protection</P><P>Integrated Framework for Obfuscation</P><P>Results</P><P>A FPGA-Based Design Technique for Trojan Isolation</P><P>A Design Infrastructure Approach to Prevent Circuit Malfunction</P><B><P>Physically Unclonable Functions: A Root-of-Trust for Hardware Security</P></B><P>Introduction</P><P>Physically Unclonable Function (PUF)</P><P>Classification of PUFs</P><P>Realization of Silicon PUFs</P><P>PUF Performance Metrics for Quality Evaluation</P><P>Secure PUF: What Makes a PUF Secure?</P><P>Applications of PUF as a Root-of-Trust</P><P>Attacks Model: How PUF Security Could Be Compromised</P><P>Looking Forward: What Lies Ahead for PUFs?</P><B><P>Genetic Programming-Based Model Building Attack on PUFs</P></B><P>Introduction</P><P>Background: Genetic Programming and RO-PUFs</P><P>Methodology</P><P>Results</P><B><P>Bibliography</P></B>
588 0 $aPrint version record.
650 0 $aComputer security.
650 0 $aData encryption (Computer science)
650 0 $aIntegrated circuits$xDesign and construction.
650 0 $aComputers$xCircuits$xDesign and construction.
650 7 $aComputer security.$2fast$0(OCoLC)fst00872484
650 7 $aComputers$xCircuits$xDesign and construction.$2fast$0(OCoLC)fst00872793
650 7 $aData encryption (Computer science)$2fast$0(OCoLC)fst00887935
650 7 $aIntegrated circuits$xDesign and construction.$2fast$0(OCoLC)fst00975545
655 4 $aElectronic books.
859 $aELD$bebook
889 $a(OCoLC)901246160
852 $aBritish Library$bHMNTS$cDRT$jELD.DS.143729
903 $aELD.DS.143729