In this thesis, a method of time-interleaving continuous-time delta-sigma modulators is investigated. The derivation of the modulator starting from a discrete-time time-interleaved structure is presented. With various simplifications, the resulting modulator has only a single-path of integrators, making it robust to DC offsets. A third-order low-pass continuous-time time-interleaved delta-sigma modulator with an oversampling ratio of 5 is designed in a 0.18mu m CMOS technology with a 1.8V supply voltage. Experimental results show that an SNDR of 57dB and a dynamic range of 60dB are obtained with a sampling frequency of 100MHz. With a sampling frequency of 200MHz, an SNDR of 49dB with a dynamic range of 55dB is achieved. The power consumption is 101mW at 100MHz, and 103 mW at 200MHz.