| Record ID | marc_oregon_summit_records/catalog_files/osu_bibs.mrc:609545805:966 |
| Source | Oregon Libraries |
| Download Link | /show-records/marc_oregon_summit_records/catalog_files/osu_bibs.mrc:609545805:966?format=raw |
LEADER: 00966nam a2200313Ia 4500
001 30134523
003 OR
008 940414s1992 xx a 000 0 eng d
035 $a10643040
040 $aORE$cORE
049 $aOREV$lbna
090 $aLD4330 1992$b.H62
090 $aLD4330 1992$b.H62
100 1 $aHo, Yui Luen.
245 10 $aProcessor memory traffic characteristics for on-chip cache /$cby Yui Luen Ho.
260 $c1992.
300 $a74 leaves, bound :$bill. ;$c29 cm.
500 $aTypescript (photocopy)
502 $aThesis (M.S.)--Oregon State University, 1992.
504 $aIncludes bibliographical references (leaves 62-67)
650 0 $aCache memory.
690 $aTheses, OSU$xElectrical and Computer Engineering.
700 1 $aHo, Jeremy Yui Luen.
907 $a.b15903801$bmulti$c-
902 $a050902
998 $b2$c981001$dm$ea$f-$g0
999 $a19940414104429.0
945 $lvge $d120000496790$e1
945 $ltsvn $d120000495990$e2