| Record ID | marc_loc_2016/BooksAll.2016.part18.utf8:173171263:1066 |
| Source | Library of Congress |
| Download Link | /show-records/marc_loc_2016/BooksAll.2016.part18.utf8:173171263:1066?format=raw |
LEADER: 01066pam a2200241 a 4500
001 88030591
003 DLC
005 19890112065203.8
008 880914s1989 maua b 00100 eng
010 $a 88030591
020 $a0898383021
050 0 $aTK7874$b.S87 1989
082 0 $a621.381/73/0724$219
245 00 $aSwitch-level timing simulation of MOS VLSI circuits /$cby Vasant B. Rao ... [et al.].
260 0 $aBoston :$bKluwer Academic Publishers,$cc1989.
300 $ax, 209 p. :$bill. ;$c25 cm.
490 1 $aThe Kluwer international series in engineering and computer science ;$vSECS 66.$aVSLI, computer architecture and digital signal processing
504 $aBibliography: p. [193]-203.
500 $aIncludes index.
650 0 $aIntegrated circuits$xVery large scale integration$xComputer simulation.
700 10 $aRao, Vasant B.
830 0 $aKluwer international series in engineering and computer science ;$vSECS 66.
830 0 $aKluwer international series in engineering and computer science.$pVLSI, computer architecture and digital signal processing.