MARC Record from marc_columbia

LEADER: 06306cam a2200745Ia 4500
001 14668993
005 20220627125652.0
006 m o d
007 cr cn|||||||||
008 090407s2009 si a ob 001 0 eng d
035 $a(OCoLC)ocn659392313
035 $a(NNC)14668993
040 $aCaPaEBR$beng$epn$cCOCUF$dOCLCQ$dN$T$dOCLCQ$dE7B$dOCLCQ$dVPI$dM6U$dOCLCQ$dYDXCP$dOCLCQ$dUA@$dOCLCF$dCRCPR$dOCLCQ$dPIFBY$dOTZ$dUAB$dERL$dOCLCQ$dCEF$dUPM$dLEAUB$dTYFRS$dUHL$dUKAHL$dOCLCO
019 $a649831396$a696629402$a991943862$a994960101$a1031049659$a1064776731
020 $a9789814241298$q(electronic bk.)
020 $a9814241296$q(electronic bk.)
020 $a9780429086335$q(electronic bk.)
020 $a0429086334$q(electronic bk.)
020 $a9780429533624$q(electronic bk. : EPUB)
020 $a0429533624$q(electronic bk. : EPUB)
020 $a9780429548321$q(electronic bk. : Mobipocket)
020 $a042954832X$q(electronic bk. : Mobipocket)
020 $z9814241288
020 $z9789814241281
035 $a(OCoLC)659392313$z(OCoLC)649831396$z(OCoLC)696629402$z(OCoLC)991943862$z(OCoLC)994960101$z(OCoLC)1031049659$z(OCoLC)1064776731
037 $a9780429086335$bTaylor & Francis
050 4 $aTK7871.99.M44$bE44 2009eb
072 7 $aTEC$x008050$2bisacsh
072 7 $aTEC$x008030$2bisacsh
072 7 $aCOM$x036000$2bisacsh
072 7 $aTEC$x021000$2bisacsh
072 7 $aTEC$x008000$2bisacsh
072 7 $aSCI$x086000$2bisacsh
072 7 $aTJFN$2bicssc
082 04 $a621.39/5$222
049 $aZCUA
245 00 $aElectronic device architectures for the nano-CMOS era :$bfrom ultimate CMOS scaling to beyond CMOS devices /$ceditor, Simon Deleonibus.
260 $aSingapore :$bPan Stanford,$c©2009.
300 $a1 online resource (xiv, 425 pages) :$billustrations (some color)
336 $atext$btxt$2rdacontent
337 $acomputer$bc$2rdamedia
338 $aonline resource$bcr$2rdacarrier
504 $aIncludes bibliographical references and index.
588 0 $aPrint version record.
505 0 $aCh. 1. Physical and technological limitations of NANOCMOS devices to the end of the roadmap and beyond / Simon Deleonibus [and others] -- ch. 2. Advanced CMOS devices on bulk and SOI : physics, modeling and characterization / Thierry Poiroux and Gilles Le Carval -- ch. 3. Devices structures and carrier transport properties of advanced CMOS using high mobility channels / Shinichi Takagi [and others] -- ch. 4. High-K gate dielectrics / Hei Wong [and others] -- ch. 5. Fabrication of source and drain : ultra shallow junction / Bunji Mizuno -- ch. 6. New interconnect schemes : end of copper, optical interconnects? / Suzanne Laval [and others] -- ch. 7. Technologies and key design issues for memory devices / Kinam Kim and Gitae Jeong -- ch. 8. FeRAM and MRAM technologies / Yoshihiro Arimoto -- ch. 9. Advanced charge storage memories : from silicon nanocrystals to molecular devices / Barbara De Salvo and Gabriel Molas -- ch. 10. Single electron devices and applications / Jacques Gautier, Xavier Jehl, and Marc Sanquer -- ch. 11. Electronic properties of organic monolayers and molecular devices / Dominique Vuillaume -- ch. 12. Carbon nanotube electronics / Vincent Derycke, Arianna Filoramo and Jean-Philippe Bourgoin -- ch. 13. Spin electronics / Kyung-Jin Lee and Sang Ho Lim -- ch. 14. The longer term : quantum information processing and communication / Philippe Jorrand.
520 $aIn this book, internationally recognized researchers give a state-of-the-art overview of the electronic device architectures required for the nano-CMOS era and beyond. Challenges relevant to the scaling of CMOS nanoelectronics are addressed through different core CMOS and memory device options in the first part of the book. The second part reviews new device concepts for nanoelectronics beyond CMOS. The book covers the fundamental limits of core CMOS, improving scaling by the introduction of new materials or processes,new architectures using SOI, multigates and multichannels, and quantum computing.
545 0 $aSimon Deleonibus (MSc 1979, PhD 1982, Paris University) was with Thomson Semiconducteurs, Grenoble, France, from 1981 to 1986 in device engineering development and then production. In 1986 he was with CEA LETI advanced device and process modules research specialising in CMOS and flash memories applications. From 1998 to 2008 he was the director of the Electronic Nanodevices Laboratory with 55 researchers under his charge. Since 2008, he is the chief scientific director of Silicon Technologies of LETI. He owns the initial patent on contact plug principle, widely used as a standard process by the semiconductor industry. He actualised the first 20-nm gate length MOSFET, the world's smallest transistor, in June 1999. He is the editor of IEEE Transactions on Electron Devices and a member of the International Technology Roadmap of Semiconductors (ITRS), of the board of directors of the Nanosciences Foundation and of The European Research Council Engineering Panel. A Fellow of the IEEE, he is its distinguished lecturer. He is also the research director of the French CEA.
650 0 $aMetal oxide semiconductors, Complementary.
650 0 $aNanoelectronics.
650 6 $aMOS complémentaires.
650 6 $aNanoélectronique.
650 7 $aTECHNOLOGY & ENGINEERING$xElectronics$xCircuits$xVLSI & ULSI.$2bisacsh
650 7 $aTECHNOLOGY & ENGINEERING$xElectronics$xCircuits$xLogic.$2bisacsh
650 7 $aCOMPUTERS$xLogic Design.$2bisacsh
650 7 $aTECHNOLOGY / Material Science$2bisacsh
650 7 $aTECHNOLOGY / Electronics / General$2bisacsh
650 7 $aSCIENCE / Life Sciences / General$2bisacsh
650 7 $aMetal oxide semiconductors, Complementary.$2fast$0(OCoLC)fst01017635
650 7 $aNanoelectronics.$2fast$0(OCoLC)fst01741867
655 0 $aElectronic books.
655 4 $aElectronic books.
700 1 $aDeleonibus, Simon.
776 08 $iPrint version:$tElectronic device architectures for the nano-CMOS era.$dSingapore : Pan Stanford ; Distributed by World Scientific, ©2009$z9814241288$w(DLC) 2009417204$w(OCoLC)213479458
856 40 $uhttp://www.columbia.edu/cgi-bin/cul/resolve?clio14668993$zTaylor & Francis eBooks
852 8 $blweb$hEBOOKS